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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir

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Canonicalize a large number of mir tests using update_mir_test_checks This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. llvm-svn: 316137
2017-10-19 07:18:12 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[globalisel] Remove redundant -global-isel option from tests that use -run-pass. NFC As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the -global-isel option is redundant when -run-pass is given. -global-isel sets up the GlobalISel passes in the pass manager but -run-pass skips that entirely and configures it's own pipeline. llvm-svn: 331603
2018-05-06 05:19:59 +08:00
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
AMDGPU/GlobalISel: Mark 32-bit integer constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33115 llvm-svn: 302919
2017-05-13 00:46:46 +08:00
---
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
name: test_constant_i32
AMDGPU/GlobalISel: Mark 32-bit integer constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33115 llvm-svn: 302919
2017-05-13 00:46:46 +08:00
body: |
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
bb.0:
AMDGPU/GlobalISel: Mark 32-bit integer constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33115 llvm-svn: 302919
2017-05-13 00:46:46 +08:00
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
; CHECK-LABEL: name: test_constant_i32
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
AMDGPU/GlobalISel: Cleanup constant legality llvm-svn: 327774
2018-03-17 23:17:48 +08:00
; CHECK: $vgpr0 = COPY [[C]](s32)
%0:_(s32) = G_CONSTANT i32 5
$vgpr0 = COPY %0
AMDGPU/GlobalISel: Mark 32-bit integer constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33115 llvm-svn: 302919
2017-05-13 00:46:46 +08:00
...
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
---
name: test_constant_i64
body: |
bb.0:
AMDGPU/GlobalISel: Mark 32-bit float constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33212 llvm-svn: 304003
2017-05-27 00:40:03 +08:00
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
; CHECK-LABEL: name: test_constant_i64
AMDGPU/GlobalISel: Cleanup constant legality llvm-svn: 327774
2018-03-17 23:17:48 +08:00
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64)
%0:_(s64) = G_CONSTANT i64 5
$vgpr0_vgpr1 = COPY %0
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
...
AMDGPU/GlobalISel: Mark 32-bit float constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33212 llvm-svn: 304003
2017-05-27 00:40:03 +08:00
---
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
name: test_fconstant_f32
AMDGPU/GlobalISel: Mark 32-bit float constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33212 llvm-svn: 304003
2017-05-27 00:40:03 +08:00
body: |
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
bb.0:
AMDGPU/GlobalISel: Mark 32-bit float constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33212 llvm-svn: 304003
2017-05-27 00:40:03 +08:00
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
; CHECK-LABEL: name: test_fconstant_f32
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
; CHECK: $vgpr0 = COPY [[C]](s32)
AMDGPU/GlobalISel: Cleanup constant legality llvm-svn: 327774
2018-03-17 23:17:48 +08:00
%0:_(s32) = G_FCONSTANT float 1.0
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$vgpr0 = COPY %0
AMDGPU/GlobalISel: Mark 32-bit float constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33212 llvm-svn: 304003
2017-05-27 00:40:03 +08:00
...
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
---
name: test_fconstant_f64
body: |
bb.0:
; CHECK-LABEL: name: test_fconstant_f64
; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64)
AMDGPU/GlobalISel: Cleanup constant legality llvm-svn: 327774
2018-03-17 23:17:48 +08:00
%0:_(s64) = G_FCONSTANT double 1.0
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
$vgpr0_vgpr1 = COPY %0
AMDGPU/GlobalISel: Cleanup constant legality llvm-svn: 327774
2018-03-17 23:17:48 +08:00
...
---
name: test_constant_1
body: |
bb.0:
; CHECK-LABEL: name: test_constant_1
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: S_ENDPGM implicit [[C]](s1)
%1:_(s1) = G_CONSTANT i1 0
S_ENDPGM implicit %1
AMDGPU/GlobalISel: Make f64 constants legal llvm-svn: 326101
2018-02-27 01:20:43 +08:00
...