maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h

224 lines
10 KiB
C
Raw Normal View History

Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Hexagon implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef HexagonINSTRUCTIONINFO_H
#define HexagonINSTRUCTIONINFO_H
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. llvm-svn: 152997
2012-03-18 02:46:09 +08:00
#include "HexagonRegisterInfo.h"
Use TSFlag bit to describe instruction properties. Creating the isPredicated TSFlag enables the code to use the property defined in the instruction format instead of using a large switch statement. llvm-svn: 150078
2012-02-09 02:25:47 +08:00
#include "MCTargetDesc/HexagonBaseInfo.h"
Hexagon: Use multiclass for Jump instructions. llvm-svn: 180885
2013-05-02 05:37:34 +08:00
#include "llvm/Target/TargetInstrInfo.h"
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
#include "llvm/Target/TargetFrameLowering.h"
Hexagon: Honor __builtin_expect by using branch probabilities. * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
2013-05-02 23:39:30 +08:00
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
#define GET_INSTRINFO_HEADER
#include "HexagonGenInstrInfo.inc"
namespace llvm {
class HexagonInstrInfo : public HexagonGenInstrInfo {
[weak vtables] Remove a bunch of weak vtables This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
2013-11-19 08:57:56 +08:00
virtual void anchor();
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
const HexagonRegisterInfo RI;
Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. llvm-svn: 183490
2013-06-07 14:19:56 +08:00
const HexagonSubtarget &Subtarget;
Hexagon: Use multiclass for Jump instructions. llvm-svn: 180885
2013-05-02 05:37:34 +08:00
typedef unsigned Opcode_t;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
public:
explicit HexagonInstrInfo(HexagonSubtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
Implement HexagonInstrInfo::analyzeCompare. llvm-svn: 174901
2013-02-12 04:04:29 +08:00
virtual bool analyzeCompare(const MachineInstr *MI,
unsigned &SrcReg, unsigned &SrcReg2,
int &Mask, int &Value) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr* MI,
const SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const;
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr* MI,
const SmallVectorImpl<unsigned> &Ops,
MachineInstr* LoadMI) const {
return 0;
}
unsigned createVR(MachineFunction* MF, MVT VT) const;
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. llvm-svn: 181235
2013-05-07 02:49:23 +08:00
virtual bool isBranch(const MachineInstr *MI) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
virtual bool isPredicable(MachineInstr *MI) const;
virtual bool
PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Cond) const;
*typo: Cyles changed to Cycles llvm-svn: 158404
2012-06-13 23:53:04 +08:00
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
unsigned ExtraPredCycles,
const BranchProbability &Probability) const;
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumTCycles, unsigned ExtraTCycles,
MachineBasicBlock &FMBB,
unsigned NumFCycles, unsigned ExtraFCycles,
const BranchProbability &Probability) const;
virtual bool isPredicated(const MachineInstr *MI) const;
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. llvm-svn: 181235
2013-05-07 02:49:23 +08:00
virtual bool isPredicated(unsigned Opcode) const;
virtual bool isPredicatedTrue(const MachineInstr *MI) const;
virtual bool isPredicatedTrue(unsigned Opcode) const;
Hexagon: Replace switch-case in isDotNewInst with TSFlags. llvm-svn: 178281
2013-03-29 03:44:04 +08:00
virtual bool isPredicatedNew(const MachineInstr *MI) const;
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. llvm-svn: 181235
2013-05-07 02:49:23 +08:00
virtual bool isPredicatedNew(unsigned Opcode) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
virtual bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const;
virtual bool
SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const;
virtual bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
virtual bool
isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
const BranchProbability &Probability) const;
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
2012-02-02 06:13:57 +08:00
virtual DFAPacketizer*
CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const;
virtual bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
bool isValidOffset(const int Opcode, const int Offset) const;
bool isValidAutoIncImm(const EVT VT, const int Offset) const;
bool isMemOp(const MachineInstr *MI) const;
bool isSpillPredRegOp(const MachineInstr *MI) const;
bool isU6_3Immediate(const int value) const;
bool isU6_2Immediate(const int value) const;
bool isU6_1Immediate(const int value) const;
bool isU6_0Immediate(const int value) const;
bool isS4_3Immediate(const int value) const;
bool isS4_2Immediate(const int value) const;
bool isS4_1Immediate(const int value) const;
bool isS4_0Immediate(const int value) const;
bool isS12_Immediate(const int value) const;
bool isU6_Immediate(const int value) const;
bool isS8_Immediate(const int value) const;
bool isS6_Immediate(const int value) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
bool isConditionalTransfer(const MachineInstr* MI) const;
Revert r155365, r155366, and r155367. All three of these have regression test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
2012-04-24 02:25:57 +08:00
bool isConditionalALU32 (const MachineInstr* MI) const;
bool isConditionalLoad (const MachineInstr* MI) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isConditionalStore(const MachineInstr* MI) const;
Hexagon: Use MO operand flags to mark constant extended instructions. llvm-svn: 176500
2013-03-06 02:51:42 +08:00
bool isNewValueInst(const MachineInstr* MI) const;
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. llvm-svn: 181235
2013-05-07 02:49:23 +08:00
bool isNewValue(const MachineInstr* MI) const;
Hexagon: Replace switch-case in isDotNewInst with TSFlags. llvm-svn: 178281
2013-03-29 03:44:04 +08:00
bool isDotNewInst(const MachineInstr* MI) const;
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. No functionality change. llvm-svn: 181628
2013-05-11 04:58:11 +08:00
int GetDotOldOp(const int opc) const;
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. llvm-svn: 181624
2013-05-11 04:27:34 +08:00
int GetDotNewOp(const MachineInstr* MI) const;
Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions. No functionality change. llvm-svn: 181535
2013-05-10 03:16:07 +08:00
int GetDotNewPredOp(MachineInstr *MI,
const MachineBranchProbabilityInfo
*MBPI) const;
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. No functionality change. llvm-svn: 181628
2013-05-11 04:58:11 +08:00
bool mayBeNewStore(const MachineInstr* MI) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
bool isDeallocRet(const MachineInstr *MI) const;
Revert r155365, r155366, and r155367. All three of these have regression test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
2012-04-24 02:25:57 +08:00
unsigned getInvertedPredicatedOpcode(const int Opc) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isExtendable(const MachineInstr* MI) const;
bool isExtended(const MachineInstr* MI) const;
bool isPostIncrement(const MachineInstr* MI) const;
bool isNewValueStore(const MachineInstr* MI) const;
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. llvm-svn: 181624
2013-05-11 04:27:34 +08:00
bool isNewValueStore(unsigned Opcode) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isNewValueJump(const MachineInstr* MI) const;
Support for Hexagon feature, New Value Jump. llvm-svn: 156698
2012-05-12 13:10:30 +08:00
bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
Hexagon: Add constant extender support framework. llvm-svn: 176358
2013-03-02 01:37:13 +08:00
void immediateExtend(MachineInstr *MI) const;
bool isConstExtended(MachineInstr *MI) const;
Hexagon: Honor __builtin_expect by using branch probabilities. * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
2013-05-02 23:39:30 +08:00
int getDotNewPredJumpOp(MachineInstr *MI,
const MachineBranchProbabilityInfo *MBPI) const;
Hexagon: Add constant extender support framework. llvm-svn: 176358
2013-03-02 01:37:13 +08:00
unsigned getAddrMode(const MachineInstr* MI) const;
bool isOperandExtended(const MachineInstr *MI,
unsigned short OperandNum) const;
unsigned short getCExtOpNum(const MachineInstr *MI) const;
int getMinValue(const MachineInstr *MI) const;
int getMaxValue(const MachineInstr *MI) const;
bool NonExtEquivalentExists (const MachineInstr *MI) const;
short getNonExtOpcode(const MachineInstr *MI) const;
Hexagon: Use multiclass for Jump instructions. llvm-svn: 180885
2013-05-02 05:37:34 +08:00
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
bool PredOpcodeHasNot(Opcode_t Opcode) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
private:
int getMatchingCondBranchOpcode(int Opc, bool sense) const;
};
}
#endif