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llvm-project/llvm/test/MC/Mips/macro-ld-sd.s

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[mips] Map SW instruction to its microMIPS R6 variant To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
2019-03-13 21:09:30 +08:00
# RUN: llvm-mc -triple mips-mti-linux-gnu -mcpu=mips32r2 \
# RUN: -show-encoding %s | FileCheck --check-prefixes=ALL,32 %s
# RUN: llvm-mc -triple mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips \
# RUN: -show-encoding %s | FileCheck --check-prefixes=ALL,MM2 %s
# RUN: llvm-mc -triple mips-mti-linux-gnu -mcpu=mips32r6 -mattr=+micromips \
# RUN: -show-encoding %s | FileCheck --check-prefixes=ALL,MM6 %s
[mips] Macro expansion for ld, sd for O32 ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
2016-10-18 22:28:00 +08:00
# RUN: llvm-mc -triple mips64-mti-linux-gnu -show-encoding %s -target-abi n64 \
# RUN: | FileCheck --check-prefixes=ALL,64 %s
# RUN: llvm-mc -triple mips64-mti-linux-gnu -show-encoding %s -target-abi n32 \
# RUN: | FileCheck --check-prefixes=ALL,64 %s
# ALL: .text
ld $8, 0($5)
# 32: lw $8, 0($5) # encoding: [0x8c,0xa8,0x00,0x00]
# 32: lw $9, 4($5) # encoding: [0x8c,0xa9,0x00,0x04]
[mips] Map SW instruction to its microMIPS R6 variant To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
2019-03-13 21:09:30 +08:00
# MM2: lw $8, 0($5) # encoding: [0xfd,0x05,0x00,0x00]
# MM2: lw $9, 4($5) # encoding: [0xfd,0x25,0x00,0x04]
# MM6: lw $8, 0($5) # encoding: [0xfd,0x05,0x00,0x00]
# MM6: lw $9, 4($5) # encoding: [0xfd,0x25,0x00,0x04]
[mips] Macro expansion for ld, sd for O32 ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
2016-10-18 22:28:00 +08:00
# 64: ld $8, 0($5) # encoding: [0xdc,0xa8,0x00,0x00]
sd $8, 0($5)
# 32: sw $8, 0($5) # encoding: [0xac,0xa8,0x00,0x00]
# 32: sw $9, 4($5) # encoding: [0xac,0xa9,0x00,0x04]
[mips] Map SW instruction to its microMIPS R6 variant To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
2019-03-13 21:09:30 +08:00
# MM2: sw $8, 0($5) # encoding: [0xf9,0x05,0x00,0x00]
# MM2: sw $9, 4($5) # encoding: [0xf9,0x25,0x00,0x04]
# MM6: sw $8, 0($5) # encoding: [0xf9,0x05,0x00,0x00]
# MM6: sw $9, 4($5) # encoding: [0xf9,0x25,0x00,0x04]
[mips] Macro expansion for ld, sd for O32 ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
2016-10-18 22:28:00 +08:00
# 64: sd $8, 0($5) # encoding: [0xfc,0xa8,0x00,0x00]
ld $8, 0($8)
# 32: lw $9, 4($8) # encoding: [0x8d,0x09,0x00,0x04]
# 32: lw $8, 0($8) # encoding: [0x8d,0x08,0x00,0x00]
[mips] Map SW instruction to its microMIPS R6 variant To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
2019-03-13 21:09:30 +08:00
# MM2: lw $9, 4($8) # encoding: [0xfd,0x28,0x00,0x04]
# MM2: lw $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]
# MM6: lw $9, 4($8) # encoding: [0xfd,0x28,0x00,0x04]
# MM6: lw $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]
llvm/test/MC/Mips/macro-ld-sd.s: Sweep a spurious character \xA0 in the test file. It might crash FileCheck. llvm-svn: 284587
2016-10-19 21:41:12 +08:00
# 64: ld $8, 0($8) # encoding: [0xdd,0x08,0x00,0x00]
[mips] Macro expansion for ld, sd for O32 ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
2016-10-18 22:28:00 +08:00
sd $8, 0($8)
# 32: sw $8, 0($8) # encoding: [0xad,0x08,0x00,0x00]
# 32: sw $9, 4($8) # encoding: [0xad,0x09,0x00,0x04]
[mips] Map SW instruction to its microMIPS R6 variant To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
2019-03-13 21:09:30 +08:00
# MM2: sw $8, 0($8) # encoding: [0xf9,0x08,0x00,0x00]
# MM2: sw $9, 4($8) # encoding: [0xf9,0x28,0x00,0x04]
# MM6: sw $8, 0($8) # encoding: [0xf9,0x08,0x00,0x00]
# MM6: sw $9, 4($8) # encoding: [0xf9,0x28,0x00,0x04]
[mips] Macro expansion for ld, sd for O32 ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
2016-10-18 22:28:00 +08:00
# 64: sd $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]