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llvm-project/llvm/test/MC/AArch64/SVE/ldff1d.s

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[AArch64][SVE] Asm: Support for contiguous, first-faulting LDFF1 (scalar+scalar) load instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45946 llvm-svn: 330697
2018-04-24 16:59:08 +08:00
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option A subsequent change will reject -long-option.
2020-03-16 07:17:52 +08:00
// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
[AArch64][SVE] Asm: Support for contiguous, first-faulting LDFF1 (scalar+scalar) load instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45946 llvm-svn: 330697
2018-04-24 16:59:08 +08:00
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ldff1d { z31.d }, p7/z, [sp]
// CHECK-INST: ldff1d { z31.d }, p7/z, [sp]
// CHECK-ENCODING: [0xff,0x7f,0xff,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 7f ff a5 <unknown>
ldff1d { z31.d }, p7/z, [sp, xzr, lsl #3]
// CHECK-INST: ldff1d { z31.d }, p7/z, [sp]
// CHECK-ENCODING: [0xff,0x7f,0xff,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 7f ff a5 <unknown>
ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x60,0xe0,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 e0 a5 <unknown>
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions. Patch [2/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46023 llvm-svn: 330928
2018-04-26 16:19:53 +08:00
ldff1d { z31.d }, p7/z, [sp, z31.d]
// CHECK-INST: ldff1d { z31.d }, p7/z, [sp, z31.d]
// CHECK-ENCODING: [0xff,0xff,0xdf,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff df c5 <unknown>
ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
// CHECK-INST: ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 ed e8 c5 <unknown>
ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
// CHECK-ENCODING: [0x55,0x75,0x95,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 95 c5 <unknown>
ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
// CHECK-ENCODING: [0x55,0x75,0xd5,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 55 75 d5 c5 <unknown>
ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
// CHECK-ENCODING: [0x00,0x60,0xa0,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 a0 c5 <unknown>
ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
// CHECK-ENCODING: [0x00,0x60,0xe0,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 e0 c5 <unknown>
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46120 llvm-svn: 331145
2018-04-30 01:33:38 +08:00
ldff1d { z31.d }, p7/z, [z31.d, #248]
// CHECK-INST: ldff1d { z31.d }, p7/z, [z31.d, #248]
// CHECK-ENCODING: [0xff,0xff,0xbf,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff bf c5 <unknown>
ldff1d { z0.d }, p0/z, [z0.d]
// CHECK-INST: ldff1d { z0.d }, p0/z, [z0.d]
// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 e0 a0 c5 <unknown>