2017-06-13 01:31:36 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
|
|
|
|
|
|
|
|
define i32 @shl48sar47(i64 %a) #0 {
|
|
|
|
; CHECK-LABEL: shl48sar47:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
; CHECK-NEXT: movswq %di, %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: addl %eax, %eax
|
2017-12-07 18:40:31 +08:00
|
|
|
; CHECK-NEXT: # kill: def %eax killed %eax killed %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
%1 = shl i64 %a, 48
|
|
|
|
%2 = ashr exact i64 %1, 47
|
|
|
|
%3 = trunc i64 %2 to i32
|
|
|
|
ret i32 %3
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @shl48sar49(i64 %a) #0 {
|
|
|
|
; CHECK-LABEL: shl48sar49:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
; CHECK-NEXT: movswq %di, %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: shrq %rax
|
2017-12-07 18:40:31 +08:00
|
|
|
; CHECK-NEXT: # kill: def %eax killed %eax killed %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
%1 = shl i64 %a, 48
|
|
|
|
%2 = ashr exact i64 %1, 49
|
|
|
|
%3 = trunc i64 %2 to i32
|
|
|
|
ret i32 %3
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @shl56sar55(i64 %a) #0 {
|
|
|
|
; CHECK-LABEL: shl56sar55:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
; CHECK-NEXT: movsbq %dil, %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: addl %eax, %eax
|
2017-12-07 18:40:31 +08:00
|
|
|
; CHECK-NEXT: # kill: def %eax killed %eax killed %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
%1 = shl i64 %a, 56
|
|
|
|
%2 = ashr exact i64 %1, 55
|
|
|
|
%3 = trunc i64 %2 to i32
|
|
|
|
ret i32 %3
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @shl56sar57(i64 %a) #0 {
|
|
|
|
; CHECK-LABEL: shl56sar57:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
; CHECK-NEXT: movsbq %dil, %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: shrq %rax
|
2017-12-07 18:40:31 +08:00
|
|
|
; CHECK-NEXT: # kill: def %eax killed %eax killed %rax
|
2016-10-17 23:38:41 +08:00
|
|
|
; CHECK-NEXT: retq
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
%1 = shl i64 %a, 56
|
|
|
|
%2 = ashr exact i64 %1, 57
|
|
|
|
%3 = trunc i64 %2 to i32
|
|
|
|
ret i32 %3
|
|
|
|
}
|
|
|
|
|
2016-10-17 23:44:59 +08:00
|
|
|
define i8 @all_sign_bit_ashr(i8 %x) {
|
|
|
|
; CHECK-LABEL: all_sign_bit_ashr:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2016-10-17 23:44:59 +08:00
|
|
|
; CHECK-NEXT: andb $1, %dil
|
|
|
|
; CHECK-NEXT: negb %dil
|
|
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%and = and i8 %x, 1
|
|
|
|
%neg = sub i8 0, %and
|
|
|
|
%sar = ashr i8 %neg, 6
|
|
|
|
ret i8 %sar
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @all_sign_bit_ashr_vec(<4 x i32> %x) {
|
|
|
|
; CHECK-LABEL: all_sign_bit_ashr_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; CHECK: # %bb.0:
|
2016-10-17 23:44:59 +08:00
|
|
|
; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
|
|
|
|
; CHECK-NEXT: pxor %xmm1, %xmm1
|
|
|
|
; CHECK-NEXT: psubd %xmm0, %xmm1
|
|
|
|
; CHECK-NEXT: movdqa %xmm1, %xmm0
|
|
|
|
; CHECK-NEXT: retq
|
|
|
|
%and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>
|
|
|
|
%neg = sub <4 x i32> zeroinitializer, %and
|
|
|
|
%sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0>
|
|
|
|
ret <4 x i32> %sar
|
|
|
|
}
|
|
|
|
|
[X86] Improve shift combining
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])
sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.
This fixes PR24373.
Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161
llvm-svn: 255761
2015-12-16 19:22:37 +08:00
|
|
|
attributes #0 = { nounwind }
|