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llvm-project/llvm/test/MC/PowerPC/future.s

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[PowerPC][Future] Add prefixed instruction paddi to future CPU Future CPU will include support for prefixed instructions. These prefixed instructions are formed by a 4 byte prefix immediately followed by a 4 byte instruction effectively making an 8 byte instruction. The new instruction paddi is a prefixed form of addi. This patch adds paddi and all of the support required for that instruction. The majority of the patch deals with supporting the new prefixed instructions. The addition of paddi is mainly to allow for testing. Differential Revision: https://reviews.llvm.org/D72569
2020-01-24 04:01:02 +08:00
# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-BE %s
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-LE %s
# CHECK-BE: paddi 1, 2, 8589934591, 0 # encoding: [0x06,0x01,0xff,0xff
# CHECK-BE-SAME: 0x38,0x22,0xff,0xff]
# CHECK-LE: paddi 1, 2, 8589934591, 0 # encoding: [0xff,0xff,0x01,0x06
# CHECK-LE-SAME: 0xff,0xff,0x22,0x38]
paddi 1, 2, 8589934591, 0
# CHECK-BE: paddi 1, 0, -8589934592, 1 # encoding: [0x06,0x12,0x00,0x00
# CHECK-BE-SAME: 0x38,0x20,0x00,0x00]
# CHECK-LE: paddi 1, 0, -8589934592, 1 # encoding: [0x00,0x00,0x12,0x06
# CHECK-LE-SAME: 0x00,0x00,0x20,0x38]
paddi 1, 0, -8589934592, 1
# CHECK-BE: pli 1, -8589934592 # encoding: [0x06,0x02,0x00,0x00
# CHECK-BE-SAME: 0x38,0x20,0x00,0x00]
# CHECK-LE: pli 1, -8589934592 # encoding: [0x00,0x00,0x02,0x06
# CHECK-LE-SAME: 0x00,0x00,0x20,0x38]
pli 1, -8589934592
# CHECK-BE: pli 1, 8589934591 # encoding: [0x06,0x01,0xff,0xff
# CHECK-BE-SAME: 0x38,0x20,0xff,0xff]
# CHECK-LE: pli 1, 8589934591 # encoding: [0xff,0xff,0x01,0x06
# CHECK-LE-SAME: 0xff,0xff,0x20,0x38]
pli 1, 8589934591
[PowerPC][Future] Add pld and pstd to future CPU Add the prefixed instructions pld and pstd to future CPU. These are load and store instructions that require new operand types that are 34 bits. This patch adds the two instructions as well as the operand types required. Note that this patch also makes a minor change to tablegen to account for the fact that some instructions are going to require shifts greater than 31 bits for the new 34 bit instructions. Differential Revision: https://reviews.llvm.org/D72574
2020-01-28 22:22:53 +08:00
# CHECK-BE: pld 1, -8589934592(3), 0 # encoding: [0x04,0x02,0x00,0x00,
# CHECK-BE-SAME: 0xe4,0x23,0x00,0x00]
# CHECK-LE: pld 1, -8589934592(3), 0 # encoding: [0x00,0x00,0x02,0x04
# CHECK-LE-SAME: 0x00,0x00,0x23,0xe4]
pld 1, -8589934592(3), 0
# CHECK-BE: pld 1, 8589934591(0), 1 # encoding: [0x04,0x11,0xff,0xff
# CHECK-BE-SAME: 0xe4,0x20,0xff,0xff]
# CHECK-LE: pld 1, 8589934591(0), 1 # encoding: [0xff,0xff,0x11,0x04,
# CHECK-LE-SAME: 0xff,0xff,0x20,0xe4]
pld 1, 8589934591(0), 1
[PowerPC][Future] Add prefixed instruction paddi to future CPU Future CPU will include support for prefixed instructions. These prefixed instructions are formed by a 4 byte prefix immediately followed by a 4 byte instruction effectively making an 8 byte instruction. The new instruction paddi is a prefixed form of addi. This patch adds paddi and all of the support required for that instruction. The majority of the patch deals with supporting the new prefixed instructions. The addition of paddi is mainly to allow for testing. Differential Revision: https://reviews.llvm.org/D72569
2020-01-24 04:01:02 +08:00