maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/lsr-static-addr.ll

43 lines
1.2 KiB
LLVM
Raw Normal View History

Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! llvm-svn: 160520
2012-07-20 02:53:21 +08:00
; RUN: llc -march=x86-64 -mcpu=generic -mtriple=x86_64-unknown-linux-gnu -relocation-model=static -asm-verbose=false < %s | FileCheck %s
; RUN: llc -march=x86-64 -mcpu=atom -mtriple=x86_64-unknown-linux-gnu -relocation-model=static -asm-verbose=false < %s | FileCheck -check-prefix=ATOM %s
Fix X86's isLegalAddressingMode to recognize that static addresses need not be RIP-relative in small mode. llvm-svn: 111917
2010-08-24 23:55:12 +08:00
; CHECK: xorl %eax, %eax
; CHECK: movsd .LCPI0_0(%rip), %xmm0
; CHECK: align
; CHECK-NEXT: BB0_2:
; CHECK-NEXT: movsd A(,%rax,8)
; CHECK-NEXT: mulsd
; CHECK-NEXT: movsd
; CHECK-NEXT: incq %rax
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! llvm-svn: 160520
2012-07-20 02:53:21 +08:00
; ATOM: xorl %eax, %eax
X86: use sub-register sequences for MOV*r0 operations Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
2013-05-30 21:19:42 +08:00
; ATOM: movsd .LCPI0_0(%rip), %xmm0
Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! llvm-svn: 160520
2012-07-20 02:53:21 +08:00
; ATOM: align
; ATOM-NEXT: BB0_2:
; ATOM-NEXT: movsd A(,%rax,8)
; ATOM-NEXT: mulsd
; ATOM-NEXT: movsd
This patch adds the X86FixupLEAs pass, which will reduce instruction latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
2013-04-26 04:29:37 +08:00
; ATOM-NEXT: leaq 1(%rax), %rax
Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! llvm-svn: 160520
2012-07-20 02:53:21 +08:00
Fix X86's isLegalAddressingMode to recognize that static addresses need not be RIP-relative in small mode. llvm-svn: 111917
2010-08-24 23:55:12 +08:00
@A = external global [0 x double]
define void @foo(i64 %n) nounwind {
entry:
%cmp5 = icmp sgt i64 %n, 0
br i1 %cmp5, label %for.body, label %for.end
for.body:
%i.06 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr [0 x double]* @A, i64 0, i64 %i.06
%tmp3 = load double* %arrayidx, align 8
%mul = fmul double %tmp3, 2.300000e+00
store double %mul, double* %arrayidx, align 8
%inc = add nsw i64 %i.06, 1
%exitcond = icmp eq i64 %inc, %n
br i1 %exitcond, label %for.end, label %for.body
for.end:
ret void
}