forked from OSchip/llvm-project
150 lines
3.7 KiB
Plaintext
150 lines
3.7 KiB
Plaintext
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# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_mla() #0 { ret void }
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define void @test_mla_v5() #1 { ret void }
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define void @test_mls() #2 { ret void }
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define void @test_no_mls() { ret void }
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attributes #0 = { "target-features"="+v6" }
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attributes #1 = { "target-features"="-v6" }
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attributes #2 = { "target-features"="+v6t2" }
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...
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---
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name: test_mla
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# CHECK-LABEL: name: test_mla
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
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; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
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; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_ADD %3, %2
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; CHECK: [[VREGR:%[0-9]+]] = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
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%r0 = COPY %4(s32)
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; CHECK: %r0 = COPY [[VREGR]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_mla_v5
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# CHECK-LABEL: name: test_mla_v5
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
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; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
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; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_ADD %3, %2
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; CHECK: [[VREGR:%[0-9]+]] = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
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%r0 = COPY %4(s32)
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; CHECK: %r0 = COPY [[VREGR]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_mls
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# CHECK-LABEL: name: test_mls
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
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; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
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; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_SUB %2, %3
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; CHECK: [[VREGR:%[0-9]+]] = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _
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%r0 = COPY %4(s32)
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; CHECK: %r0 = COPY [[VREGR]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_no_mls
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# CHECK-LABEL: name: test_no_mls
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
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; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
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; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_SUB %2, %3
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; CHECK: [[VREGM:%[0-9]+]] = MULv5 [[VREGX]], [[VREGY]], 14, _, _
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; CHECK: [[VREGR:%[0-9]+]] = SUBrr [[VREGZ]], [[VREGM]], 14, _, _
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%r0 = COPY %4(s32)
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; CHECK: %r0 = COPY [[VREGR]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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