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llvm-project/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll

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[Power9] Exploit move and splat instructions for build_vector improvement This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
2016-09-23 21:25:31 +08:00
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-BE
@Globi = external global i32, align 4
@Globf = external global float, align 4
define <2 x i64> @test1(i64 %a, i64 %b) {
entry:
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. llvm-svn: 283190
2016-10-04 14:59:23 +08:00
; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp
; which will happen in a subsequent patch.
[Power9] Exploit move and splat instructions for build_vector improvement This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
2016-09-23 21:25:31 +08:00
; CHECK-LABEL: test1
[PowerPC] Improvements for BUILD_VECTOR Vol. 1 This patch corresponds to review: https://reviews.llvm.org/D25912 This is the first patch in a series of 4 that improve the lowering and combining for BUILD_VECTOR nodes on PowerPC. llvm-svn: 288152
2016-11-30 00:11:34 +08:00
; CHECK: mtvsrdd 34, 4, 3
[Power9] Exploit move and splat instructions for build_vector improvement This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
2016-09-23 21:25:31 +08:00
; CHECK-BE-LABEL: test1
[PowerPC] Improvements for BUILD_VECTOR Vol. 1 This patch corresponds to review: https://reviews.llvm.org/D25912 This is the first patch in a series of 4 that improve the lowering and combining for BUILD_VECTOR nodes on PowerPC. llvm-svn: 288152
2016-11-30 00:11:34 +08:00
; CHECK-BE: mtvsrdd 34, 3, 4
[Power9] Exploit move and splat instructions for build_vector improvement This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
2016-09-23 21:25:31 +08:00
%vecins = insertelement <2 x i64> undef, i64 %a, i32 0
%vecins1 = insertelement <2 x i64> %vecins, i64 %b, i32 1
ret <2 x i64> %vecins1
}
define i64 @test2(<2 x i64> %a) {
entry:
; CHECK-LABEL: test2
; CHECK: mfvsrld 3, 34
%0 = extractelement <2 x i64> %a, i32 0
ret i64 %0
}
define i64 @test3(<2 x i64> %a) {
entry:
; CHECK-BE-LABEL: test3
; CHECK-BE: mfvsrld 3, 34
%0 = extractelement <2 x i64> %a, i32 1
ret i64 %0
}
define <4 x i32> @test4(i32* nocapture readonly %in) {
entry:
; CHECK-LABEL: test4
; CHECK: lxvwsx 34, 0, 3
; CHECK-NOT: xxspltw
; CHECK-BE-LABEL: test4
; CHECK-BE: lxvwsx 34, 0, 3
; CHECK-BE-NOT: xxspltw
%0 = load i32, i32* %in, align 4
%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat
}
define <4 x float> @test5(float* nocapture readonly %in) {
entry:
; CHECK-LABEL: test5
; CHECK: lxvwsx 34, 0, 3
; CHECK-NOT: xxspltw
; CHECK-BE-LABEL: test5
; CHECK-BE: lxvwsx 34, 0, 3
; CHECK-BE-NOT: xxspltw
%0 = load float, float* %in, align 4
%splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %splat.splat
}
define <4 x i32> @test6() {
entry:
; CHECK-LABEL: test6
; CHECK: addis
; CHECK: ld [[TOC:[0-9]+]], .LC0
; CHECK: lxvwsx 34, 0, 3
; CHECK-NOT: xxspltw
; CHECK-BE-LABEL: test6
; CHECK-BE: addis
; CHECK-BE: ld [[TOC:[0-9]+]], .LC0
; CHECK-BE: lxvwsx 34, 0, 3
; CHECK-BE-NOT: xxspltw
%0 = load i32, i32* @Globi, align 4
%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat
}
define <4 x float> @test7() {
entry:
; CHECK-LABEL: test7
; CHECK: addis
; CHECK: ld [[TOC:[0-9]+]], .LC1
; CHECK: lxvwsx 34, 0, 3
; CHECK-NOT: xxspltw
; CHECK-BE-LABEL: test7
; CHECK-BE: addis
; CHECK-BE: ld [[TOC:[0-9]+]], .LC1
; CHECK-BE: lxvwsx 34, 0, 3
; CHECK-BE-NOT: xxspltw
%0 = load float, float* @Globf, align 4
%splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %splat.splat
}
define <16 x i8> @test8() {
entry:
; CHECK-LABEL: test8
; CHECK: xxlxor 34, 34, 34
; CHECK-BE-LABEL: test8
; CHECK-BE: xxlxor 34, 34, 34
ret <16 x i8> zeroinitializer
}
define <16 x i8> @test9() {
entry:
; CHECK-LABEL: test9
; CHECK: xxspltib 34, 1
; CHECK-BE-LABEL: test9
; CHECK-BE: xxspltib 34, 1
ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
}
define <16 x i8> @test10() {
entry:
; CHECK-LABEL: test10
; CHECK: xxspltib 34, 127
; CHECK-BE-LABEL: test10
; CHECK-BE: xxspltib 34, 127
ret <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>
}
define <16 x i8> @test11() {
entry:
; CHECK-LABEL: test11
; CHECK: xxspltib 34, 128
; CHECK-BE-LABEL: test11
; CHECK-BE: xxspltib 34, 128
ret <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
}
define <16 x i8> @test12() {
entry:
; CHECK-LABEL: test12
; CHECK: xxspltib 34, 255
; CHECK-BE-LABEL: test12
; CHECK-BE: xxspltib 34, 255
ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
}
define <16 x i8> @test13() {
entry:
; CHECK-LABEL: test13
; CHECK: xxspltib 34, 129
; CHECK-BE-LABEL: test13
; CHECK-BE: xxspltib 34, 129
ret <16 x i8> <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>
}
[Power9] Allow AnyExt immediates for XXSPLTIB In some situations, the BUILD_VECTOR node that builds a v18i8 vector by a splat of an i8 constant will end up with signed 8-bit values and other situations, it'll end up with unsigned ones. Handle both situations. Fixes PR31340. llvm-svn: 289804
2016-12-15 19:16:20 +08:00
define <16 x i8> @test13E127() {
entry:
; CHECK-LABEL: test13E127
; CHECK: xxspltib 34, 200
; CHECK-BE-LABEL: test13E127
; CHECK-BE: xxspltib 34, 200
ret <16 x i8> <i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200, i8 200>
}
[Power9] Exploit move and splat instructions for build_vector improvement This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
2016-09-23 21:25:31 +08:00
define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) {
entry:
; CHECK-LABEL: test14
; CHECK: lwz [[LD:[0-9]+]],
[PowerPC] Improvements for BUILD_VECTOR Vol. 4 This is the final patch in the series of patches that improves BUILD_VECTOR handling on PowerPC. This adds a few peephole optimizations to remove redundant instructions. It also adds a large test case which encompasses a large set of code patterns that build vectors - this test case was the motivator for this series of patches. Differential Revision: https://reviews.llvm.org/D26066 llvm-svn: 288800
2016-12-06 19:47:14 +08:00
; CHECK: mtvsrws 34, [[LD]]
[Power9] Exploit move and splat instructions for build_vector improvement This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
2016-09-23 21:25:31 +08:00
; CHECK-BE-LABEL: test14
; CHECK-BE: lwz [[LD:[0-9]+]],
[PowerPC] Improvements for BUILD_VECTOR Vol. 4 This is the final patch in the series of patches that improves BUILD_VECTOR handling on PowerPC. This adds a few peephole optimizations to remove redundant instructions. It also adds a large test case which encompasses a large set of code patterns that build vectors - this test case was the motivator for this series of patches. Differential Revision: https://reviews.llvm.org/D26066 llvm-svn: 288800
2016-12-06 19:47:14 +08:00
; CHECK-BE: mtvsrws 34, [[LD]]
[Power9] Exploit move and splat instructions for build_vector improvement This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. llvm-svn: 282246
2016-09-23 21:25:31 +08:00
%0 = load i32, i32* %b, align 4
%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
%1 = add i32 %0, 5
store i32 %1, i32* %b, align 4
ret <4 x i32> %splat.splat
}