2017-01-25 06:02:15 +08:00
|
|
|
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
2016-12-10 08:39:12 +08:00
|
|
|
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
|
|
|
|
|
|
|
|
|
; FIXME: Merge into imm.ll
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_neg_0.0_i16:
|
|
|
|
|
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x8000{{$}}
|
|
|
|
|
; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_neg_0.0_i16(i16 addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store volatile i16 -32768, i16 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_0.0_f16:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_0.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 0.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_imm_neg_0.0_f16:
|
|
|
|
|
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x8000{{$}}
|
|
|
|
|
; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_imm_neg_0.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half -0.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_0.5_f16:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3800{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_0.5_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 0.5, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_m_0.5_f16:
|
|
|
|
|
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb800{{$}}
|
|
|
|
|
; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffb800{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_m_0.5_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half -0.5, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_1.0_f16:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c00{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_1.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 1.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_m_1.0_f16:
|
|
|
|
|
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbc00{{$}}
|
|
|
|
|
; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffbc00{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_m_1.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half -1.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_2.0_f16:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4000{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_2.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 2.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_m_2.0_f16:
|
|
|
|
|
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc000{{$}}
|
|
|
|
|
; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffc000{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_m_2.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half -2.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_4.0_f16:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4400{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_4.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 4.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_m_4.0_f16:
|
|
|
|
|
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc400{{$}}
|
|
|
|
|
; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffc400{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_m_4.0_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half -4.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_inv_2pi_f16:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3118{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_inv_2pi_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 0xH3118, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_inline_imm_m_inv_2pi_f16:
|
|
|
|
|
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb118{{$}}
|
|
|
|
|
; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffb118{{$}}
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_inline_imm_m_inv_2pi_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 0xHB118, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}store_literal_imm_f16:
|
|
|
|
|
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x6c00
|
|
|
|
|
; GCN: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @store_literal_imm_f16(half addrspace(1)* %out) {
|
2016-12-10 08:39:12 +08:00
|
|
|
store half 4096.0, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_0.0_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 0{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_0.0_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 0.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_0.5_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 0.5{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_0.5_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 0.5
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_0.5_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], -0.5{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_neg_0.5_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, -0.5
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_1.0_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 1.0{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_1.0_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 1.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_1.0_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], -1.0{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_neg_1.0_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, -1.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_2.0_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 2.0{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_2.0_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 2.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_2.0_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], -2.0{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_neg_2.0_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, -2.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_4.0_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 4.0{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_4.0_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 4.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_4.0_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], -4.0{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_neg_4.0_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, -4.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}commute_add_inline_imm_0.5_f16:
|
|
|
|
|
; VI: buffer_load_ushort [[VAL:v[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
|
|
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @commute_add_inline_imm_0.5_f16(half addrspace(1)* %out, half addrspace(1)* %in) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%x = load half, half addrspace(1)* %in
|
|
|
|
|
%y = fadd half %x, 0.5
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}commute_add_literal_f16:
|
|
|
|
|
; VI: buffer_load_ushort [[VAL:v[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0x6400, [[VAL]]
|
|
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @commute_add_literal_f16(half addrspace(1)* %out, half addrspace(1)* %in) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%x = load half, half addrspace(1)* %in
|
|
|
|
|
%y = fadd half %x, 1024.0
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_1_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 1{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_1_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 0xH0001
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_2_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 2{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_2_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 0xH0002
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_16_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 16{{$}}
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_16_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 0xH0010
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_1_f16:
|
2018-12-23 01:10:31 +08:00
|
|
|
; VI: v_add_u16_e32 [[REG:v[0-9]+]], -1, [[REG:v[0-9]+]]
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_neg_1_f16(half addrspace(1)* %out, i16 addrspace(1)* %in) {
|
|
|
|
|
%x = load i16, i16 addrspace(1)* %in
|
|
|
|
|
%y = add i16 %x, -1
|
2018-03-20 03:23:53 +08:00
|
|
|
%ybc = bitcast i16 %y to half
|
|
|
|
|
store half %ybc, half addrspace(1)* %out
|
2016-12-10 08:39:12 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_2_f16:
|
2018-12-23 01:10:31 +08:00
|
|
|
; VI: v_add_u16_e32 [[REG:v[0-9]+]], -2, [[REG:v[0-9]+]]
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_neg_2_f16(half addrspace(1)* %out, i16 addrspace(1)* %in) {
|
|
|
|
|
%x = load i16, i16 addrspace(1)* %in
|
|
|
|
|
%y = add i16 %x, -2
|
2018-03-20 03:23:53 +08:00
|
|
|
%ybc = bitcast i16 %y to half
|
|
|
|
|
store half %ybc, half addrspace(1)* %out
|
2016-12-10 08:39:12 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_neg_16_f16:
|
2018-12-23 01:10:31 +08:00
|
|
|
; VI: v_add_u16_e32 [[REG:v[0-9]+]], -16, [[REG:v[0-9]+]]
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_neg_16_f16(half addrspace(1)* %out, i16 addrspace(1)* %in) {
|
|
|
|
|
%x = load i16, i16 addrspace(1)* %in
|
|
|
|
|
%y = add i16 %x, -16
|
2018-03-20 03:23:53 +08:00
|
|
|
%ybc = bitcast i16 %y to half
|
|
|
|
|
store half %ybc, half addrspace(1)* %out
|
2016-12-10 08:39:12 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_63_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 63
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_63_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 0xH003F
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}add_inline_imm_64_f16:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
; VI: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 64
|
2016-12-10 08:39:12 +08:00
|
|
|
; VI: buffer_store_short [[REG]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @add_inline_imm_64_f16(half addrspace(1)* %out, half %x) {
|
2016-12-10 08:39:12 +08:00
|
|
|
%y = fadd half %x, 0xH0040
|
|
|
|
|
store half %y, half addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|