2013-05-07 00:15:19 +08:00
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//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Basic SystemZ instruction definition
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//===----------------------------------------------------------------------===//
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class InstSystemZ<int size, dag outs, dag ins, string asmstr,
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list<dag> pattern> : Instruction {
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let Namespace = "SystemZ";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let Size = size;
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let Pattern = pattern;
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let AsmString = asmstr;
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2013-07-03 17:19:58 +08:00
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// Some instructions come in pairs, one having a 12-bit displacement
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// and the other having a 20-bit displacement. Both instructions in
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// the pair have the same DispKey and their DispSizes are "12" and "20"
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// respectively.
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string DispKey = "";
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string DispSize = "none";
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2013-05-07 00:15:19 +08:00
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2013-07-03 18:10:02 +08:00
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// Many register-based <INSN>R instructions have a memory-based <INSN>
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2016-11-09 02:36:31 +08:00
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// counterpart. OpKey uniquely identifies <INSN>R, while OpType is
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2013-07-03 18:10:02 +08:00
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// "reg" for <INSN>R and "mem" for <INSN>.
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string OpKey = "";
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string OpType = "none";
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2013-07-20 00:12:08 +08:00
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// Many distinct-operands instructions have older 2-operand equivalents.
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// NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
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// with NumOpsValue being "2" or "3" as appropriate.
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string NumOpsKey = "";
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string NumOpsValue = "none";
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2013-05-07 00:15:19 +08:00
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// True if this instruction is a simple D(X,B) load of a register
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// (with no sign or zero extension).
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bit SimpleBDXLoad = 0;
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// True if this instruction is a simple D(X,B) store of a register
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// (with no truncation).
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bit SimpleBDXStore = 0;
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// True if this instruction has a 20-bit displacement field.
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bit Has20BitOffset = 0;
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// True if addresses in this instruction have an index register.
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bit HasIndex = 0;
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// True if this is a 128-bit pseudo instruction that combines two 64-bit
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// operations.
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bit Is128Bit = 0;
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2013-07-03 18:10:02 +08:00
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// The access size of all memory operands in bytes, or 0 if not known.
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bits<5> AccessBytes = 0;
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2013-08-01 18:39:40 +08:00
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// If the instruction sets CC to a useful value, this gives the mask
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// of all possible CC results. The mask has the same form as
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// SystemZ::CCMASK_*.
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bits<4> CCValues = 0;
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2013-08-07 19:10:06 +08:00
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// The subset of CCValues that have the same meaning as they would after
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// a comparison of the first operand against zero.
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bits<4> CompareZeroCCMask = 0;
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2013-08-01 18:39:40 +08:00
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// True if the instruction is conditional and if the CC mask operand
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// comes first (as for BRC, etc.).
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bit CCMaskFirst = 0;
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// Similar, but true if the CC mask operand comes last (as for LOC, etc.).
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bit CCMaskLast = 0;
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// True if the instruction is the "logical" rather than "arithmetic" form,
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// in cases where a distinction exists.
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bit IsLogical = 0;
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let TSFlags{0} = SimpleBDXLoad;
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let TSFlags{1} = SimpleBDXStore;
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let TSFlags{2} = Has20BitOffset;
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let TSFlags{3} = HasIndex;
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let TSFlags{4} = Is128Bit;
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let TSFlags{9-5} = AccessBytes;
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let TSFlags{13-10} = CCValues;
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2013-08-07 19:10:06 +08:00
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let TSFlags{17-14} = CompareZeroCCMask;
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let TSFlags{18} = CCMaskFirst;
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let TSFlags{19} = CCMaskLast;
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let TSFlags{20} = IsLogical;
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2013-05-07 00:15:19 +08:00
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}
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//===----------------------------------------------------------------------===//
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// Mappings between instructions
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//===----------------------------------------------------------------------===//
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// Return the version of an instruction that has an unsigned 12-bit
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// displacement.
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def getDisp12Opcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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2013-07-03 17:19:58 +08:00
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let RowFields = ["DispKey"];
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let ColFields = ["DispSize"];
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2013-05-07 00:15:19 +08:00
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let KeyCol = ["20"];
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let ValueCols = [["12"]];
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}
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// Return the version of an instruction that has a signed 20-bit displacement.
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def getDisp20Opcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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2013-07-03 17:19:58 +08:00
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let RowFields = ["DispKey"];
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let ColFields = ["DispSize"];
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2013-05-07 00:15:19 +08:00
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let KeyCol = ["12"];
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let ValueCols = [["20"]];
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}
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2013-07-20 00:12:08 +08:00
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// Return the memory form of a register instruction.
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2013-07-03 18:10:02 +08:00
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def getMemOpcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["OpKey"];
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let ColFields = ["OpType"];
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let KeyCol = ["reg"];
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let ValueCols = [["mem"]];
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}
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2013-07-20 00:12:08 +08:00
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// Return the 3-operand form of a 2-operand instruction.
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def getThreeOperandOpcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["NumOpsKey"];
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let ColFields = ["NumOpsValue"];
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let KeyCol = ["2"];
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let ValueCols = [["3"]];
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}
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2013-05-07 00:15:19 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction formats
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//===----------------------------------------------------------------------===//
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//
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// Formats are specified using operand field declarations of the form:
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//
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2013-05-14 17:28:21 +08:00
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// bits<4> Rn : register input or output for operand n
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2015-05-06 03:23:40 +08:00
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// bits<5> Vn : vector register input or output for operand n
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2013-05-14 17:28:21 +08:00
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// bits<m> In : immediate value of width m for operand n
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// bits<4> BDn : address operand n, which has a base and a displacement
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// bits<m> XBDn : address operand n, which has an index, a base and a
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// displacement
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2015-05-06 03:23:40 +08:00
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// bits<m> VBDn : address operand n, which has a vector index, a base and a
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// displacement
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2013-05-14 17:28:21 +08:00
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// bits<4> Xn : index register for address operand n
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// bits<4> Mn : mode value for operand n
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2013-05-07 00:15:19 +08:00
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//
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2013-05-14 17:28:21 +08:00
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// The operand numbers ("n" in the list above) follow the architecture manual.
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// Assembly operands sometimes have a different order; in particular, R3 often
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// is often written between operands 1 and 2.
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2013-05-07 00:15:19 +08:00
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//
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//===----------------------------------------------------------------------===//
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2016-08-05 23:14:34 +08:00
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class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<2, outs, ins, asmstr, pattern> {
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field bits<16> Inst;
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field bits<16> SoftFail = 0;
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let Inst = op;
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}
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2016-04-11 22:35:39 +08:00
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class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<2, outs, ins, asmstr, pattern> {
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field bits<16> Inst;
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field bits<16> SoftFail = 0;
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bits<8> I1;
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let Inst{15-8} = op;
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let Inst{7-0} = I1;
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}
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2016-11-28 22:01:51 +08:00
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class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> I1;
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bits<4> I2;
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let Inst{31-16} = op;
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let Inst{15-8} = 0;
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let Inst{7-4} = I1;
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let Inst{3-0} = I2;
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}
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class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> M1;
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bits<12> RI2;
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bits<24> RI3;
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let Inst{47-40} = op;
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let Inst{39-36} = M1;
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let Inst{35-24} = RI2;
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let Inst{23-0} = RI3;
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}
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2016-11-09 02:32:50 +08:00
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class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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2013-05-07 00:15:19 +08:00
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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2013-05-14 18:17:52 +08:00
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field bits<32> SoftFail = 0;
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2013-05-07 00:15:19 +08:00
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bits<4> R1;
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bits<16> I2;
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let Inst{31-24} = op{11-4};
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let Inst{23-20} = R1;
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let Inst{19-16} = op{3-0};
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let Inst{15-0} = I2;
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}
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2016-11-09 02:30:50 +08:00
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class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> R1;
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bits<16> RI2;
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let Inst{31-24} = op{11-4};
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let Inst{23-20} = R1;
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let Inst{19-16} = op{3-0};
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let Inst{15-0} = RI2;
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}
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class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> M1;
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bits<16> RI2;
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let Inst{31-24} = op{11-4};
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let Inst{23-20} = M1;
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let Inst{19-16} = op{3-0};
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let Inst{15-0} = RI2;
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}
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2016-06-11 03:58:10 +08:00
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class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<16> I2;
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bits<4> M3;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = 0;
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let Inst{31-16} = I2;
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let Inst{15-12} = M3;
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let Inst{11-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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2013-05-28 18:41:11 +08:00
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class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R2;
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bits<4> M3;
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bits<16> RI4;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R2;
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let Inst{31-16} = RI4;
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let Inst{15-12} = M3;
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let Inst{11-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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2013-05-29 19:58:52 +08:00
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class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<8> I2;
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bits<4> M3;
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bits<16> RI4;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = M3;
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let Inst{31-16} = RI4;
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let Inst{15-8} = I2;
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let Inst{7-0} = op{7-0};
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}
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2013-07-20 00:32:12 +08:00
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class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R3;
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bits<16> I2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R3;
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let Inst{31-16} = I2;
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let Inst{15-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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2016-11-28 21:40:08 +08:00
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class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R3;
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bits<16> RI2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R3;
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let Inst{31-16} = RI2;
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|
|
let Inst{15-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
bits<8> I3;
|
|
|
|
bits<8> I4;
|
|
|
|
bits<8> I5;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = R2;
|
|
|
|
let Inst{31-24} = I3;
|
|
|
|
let Inst{23-16} = I4;
|
|
|
|
let Inst{15-8} = I5;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> M3;
|
|
|
|
bits<16> I2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = M3;
|
|
|
|
let Inst{31-16} = I2;
|
|
|
|
let Inst{15-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:32:50 +08:00
|
|
|
class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
2013-05-07 00:15:19 +08:00
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<32> I2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{11-4};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = op{3-0};
|
|
|
|
let Inst{31-0} = I2;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<32> RI2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{11-4};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = op{3-0};
|
|
|
|
let Inst{31-0} = RI2;
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> M1;
|
|
|
|
bits<32> RI2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{11-4};
|
|
|
|
let Inst{39-36} = M1;
|
|
|
|
let Inst{35-32} = op{3-0};
|
|
|
|
let Inst{31-0} = RI2;
|
|
|
|
}
|
|
|
|
|
2016-04-04 22:26:43 +08:00
|
|
|
class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<8> I2;
|
|
|
|
bits<4> M3;
|
|
|
|
bits<16> BD4;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = M3;
|
|
|
|
let Inst{31-16} = BD4;
|
|
|
|
let Inst{15-8} = I2;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<2, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<16> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<16> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
|
|
|
|
let Inst{15-8} = op;
|
|
|
|
let Inst{7-4} = R1;
|
|
|
|
let Inst{3-0} = R2;
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<32> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R3;
|
|
|
|
bits<4> R2;
|
|
|
|
|
|
|
|
let Inst{31-16} = op;
|
|
|
|
let Inst{15-12} = R1;
|
|
|
|
let Inst{11-8} = 0;
|
|
|
|
let Inst{7-4} = R3;
|
|
|
|
let Inst{3-0} = R2;
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<32> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
|
|
|
|
let Inst{31-16} = op;
|
|
|
|
let Inst{15-8} = 0;
|
|
|
|
let Inst{7-4} = R1;
|
|
|
|
let Inst{3-0} = R2;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:36:31 +08:00
|
|
|
class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
2013-05-07 00:15:19 +08:00
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<32> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
bits<4> R3;
|
2016-11-09 02:36:31 +08:00
|
|
|
bits<4> M4;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let Inst{31-16} = op;
|
|
|
|
let Inst{15-12} = R3;
|
2016-11-09 02:36:31 +08:00
|
|
|
let Inst{11-8} = M4;
|
|
|
|
let Inst{7-4} = R1;
|
|
|
|
let Inst{3-0} = R2;
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
|
|
|
field bits<32> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
bits<4> R3;
|
|
|
|
bits<4> M4;
|
|
|
|
|
|
|
|
let Inst{31-16} = op;
|
|
|
|
let Inst{15-12} = R3;
|
|
|
|
let Inst{11-8} = M4;
|
2013-05-07 00:15:19 +08:00
|
|
|
let Inst{7-4} = R1;
|
|
|
|
let Inst{3-0} = R2;
|
|
|
|
}
|
|
|
|
|
2016-06-11 03:58:10 +08:00
|
|
|
class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
|
|
|
field bits<32> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
bits<4> M3;
|
|
|
|
|
|
|
|
let Inst{31-16} = op;
|
|
|
|
let Inst{15-12} = M3;
|
|
|
|
let Inst{11-8} = 0;
|
|
|
|
let Inst{7-4} = R1;
|
|
|
|
let Inst{3-0} = R2;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:36:31 +08:00
|
|
|
class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
|
|
|
field bits<32> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
bits<4> M3;
|
|
|
|
bits<4> M4;
|
|
|
|
|
|
|
|
let Inst{31-16} = op;
|
|
|
|
let Inst{15-12} = M3;
|
|
|
|
let Inst{11-8} = M4;
|
|
|
|
let Inst{7-4} = R1;
|
|
|
|
let Inst{3-0} = R2;
|
|
|
|
}
|
|
|
|
|
2016-04-04 22:26:43 +08:00
|
|
|
class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R2;
|
|
|
|
bits<4> M3;
|
|
|
|
bits<16> BD4;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = R2;
|
|
|
|
let Inst{31-16} = BD4;
|
|
|
|
let Inst{15-12} = M3;
|
|
|
|
let Inst{11-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:32:50 +08:00
|
|
|
class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
2013-05-07 00:15:19 +08:00
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<32> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<20> XBD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let Inst{31-24} = op;
|
|
|
|
let Inst{23-20} = R1;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{19-0} = XBD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let HasIndex = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
|
|
|
field bits<32> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> M1;
|
|
|
|
bits<20> XBD2;
|
|
|
|
|
|
|
|
let Inst{31-24} = op;
|
|
|
|
let Inst{23-20} = M1;
|
|
|
|
let Inst{19-0} = XBD2;
|
|
|
|
|
|
|
|
let HasIndex = 1;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<20> XBD2;
|
2015-05-06 03:23:40 +08:00
|
|
|
bits<4> M3;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{35-16} = XBD2;
|
2015-05-06 03:23:40 +08:00
|
|
|
let Inst{15-12} = M3;
|
|
|
|
let Inst{11-8} = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
|
|
|
|
let HasIndex = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R3;
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<20> XBD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R3;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{35-16} = XBD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
let Inst{15-12} = R1;
|
|
|
|
let Inst{11-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
|
|
|
|
let HasIndex = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:32:50 +08:00
|
|
|
class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
2013-05-07 00:15:19 +08:00
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<28> XBD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{35-8} = XBD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
let HasIndex = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> M1;
|
|
|
|
bits<28> XBD2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = M1;
|
|
|
|
let Inst{35-8} = XBD2;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
let HasIndex = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:32:50 +08:00
|
|
|
class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
2013-05-07 00:15:19 +08:00
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<32> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R3;
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<16> BD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let Inst{31-24} = op;
|
|
|
|
let Inst{23-20} = R1;
|
|
|
|
let Inst{19-16} = R3;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{15-0} = BD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
|
|
|
field bits<32> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> M3;
|
|
|
|
bits<16> BD2;
|
|
|
|
|
|
|
|
let Inst{31-24} = op;
|
|
|
|
let Inst{23-20} = R1;
|
|
|
|
let Inst{19-16} = M3;
|
|
|
|
let Inst{15-0} = BD2;
|
|
|
|
}
|
|
|
|
|
2016-08-05 23:14:34 +08:00
|
|
|
class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
|
|
|
field bits<32> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R3;
|
|
|
|
bits<16> RI2;
|
|
|
|
|
|
|
|
let Inst{31-24} = op;
|
|
|
|
let Inst{23-20} = R1;
|
|
|
|
let Inst{19-16} = R3;
|
|
|
|
let Inst{15-0} = RI2;
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:42:45 +08:00
|
|
|
class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<20> BDL1;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = BDL1{19-16};
|
|
|
|
let Inst{35-32} = 0;
|
|
|
|
let Inst{31-16} = BDL1{15-0};
|
|
|
|
let Inst{15-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:32:50 +08:00
|
|
|
class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
2013-05-07 00:15:19 +08:00
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> R3;
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<24> BD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = R3;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{31-8} = BD2;
|
2013-05-07 00:15:19 +08:00
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<4> M3;
|
|
|
|
bits<24> BD2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = M3;
|
|
|
|
let Inst{31-8} = BD2;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<4, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<32> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<32> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<16> BD1;
|
2013-05-07 00:15:19 +08:00
|
|
|
bits<8> I2;
|
|
|
|
|
|
|
|
let Inst{31-24} = op;
|
|
|
|
let Inst{23-16} = I2;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{15-0} = BD1;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<16> BD1;
|
2013-05-07 00:15:19 +08:00
|
|
|
bits<16> I2;
|
|
|
|
|
|
|
|
let Inst{47-32} = op;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{31-16} = BD1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let Inst{15-0} = I2;
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
2013-05-14 18:17:52 +08:00
|
|
|
field bits<48> SoftFail = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2013-05-14 17:28:21 +08:00
|
|
|
bits<24> BD1;
|
2013-05-07 00:15:19 +08:00
|
|
|
bits<8> I2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-32} = I2;
|
2013-05-14 17:28:21 +08:00
|
|
|
let Inst{31-8} = BD1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-28 22:01:51 +08:00
|
|
|
class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> M1;
|
|
|
|
bits<16> RI2;
|
|
|
|
bits<16> BD3;
|
|
|
|
|
|
|
|
let Inst{47-40} = op;
|
|
|
|
let Inst{39-36} = M1;
|
|
|
|
let Inst{35-32} = 0;
|
|
|
|
let Inst{31-16} = BD3;
|
|
|
|
let Inst{15-0} = RI2;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:32:50 +08:00
|
|
|
class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
2013-07-02 22:56:45 +08:00
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<24> BDL1;
|
|
|
|
bits<16> BD2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op;
|
|
|
|
let Inst{39-16} = BDL1;
|
|
|
|
let Inst{15-0} = BD2;
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:42:45 +08:00
|
|
|
class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<20> BDL1;
|
|
|
|
bits<20> BDL2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op;
|
|
|
|
let Inst{39-36} = BDL1{19-16};
|
|
|
|
let Inst{35-32} = BDL2{19-16};
|
|
|
|
let Inst{31-16} = BDL1{15-0};
|
|
|
|
let Inst{15-0} = BDL2{15-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<20> BDL1;
|
|
|
|
bits<16> BD2;
|
|
|
|
bits<4> I3;
|
|
|
|
|
|
|
|
let Inst{47-40} = op;
|
|
|
|
let Inst{39-36} = BDL1{19-16};
|
|
|
|
let Inst{35-32} = I3;
|
|
|
|
let Inst{31-16} = BDL1{15-0};
|
|
|
|
let Inst{15-0} = BD2;
|
|
|
|
}
|
|
|
|
|
2016-08-05 23:14:34 +08:00
|
|
|
class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
2016-10-31 22:21:36 +08:00
|
|
|
bits<20> RBD1;
|
2016-08-05 23:14:34 +08:00
|
|
|
bits<16> BD2;
|
|
|
|
bits<4> R3;
|
|
|
|
|
|
|
|
let Inst{47-40} = op;
|
2016-10-31 22:21:36 +08:00
|
|
|
let Inst{39-36} = RBD1{19-16};
|
2016-08-05 23:14:34 +08:00
|
|
|
let Inst{35-32} = R3;
|
2016-10-31 22:21:36 +08:00
|
|
|
let Inst{31-16} = RBD1{15-0};
|
2016-08-05 23:14:34 +08:00
|
|
|
let Inst{15-0} = BD2;
|
|
|
|
}
|
|
|
|
|
2016-12-03 02:24:16 +08:00
|
|
|
class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<16> BD2;
|
|
|
|
bits<4> R3;
|
|
|
|
bits<16> BD4;
|
|
|
|
|
|
|
|
let Inst{47-40} = op;
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = R3;
|
|
|
|
let Inst{31-16} = BD2;
|
|
|
|
let Inst{15-0} = BD4;
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:42:45 +08:00
|
|
|
class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<16> BD1;
|
|
|
|
bits<24> BDL2;
|
|
|
|
|
|
|
|
let Inst{47-40} = op;
|
|
|
|
let Inst{39-32} = BDL2{23-16};
|
|
|
|
let Inst{31-16} = BD1;
|
|
|
|
let Inst{15-0} = BDL2{15-0};
|
|
|
|
}
|
|
|
|
|
2016-08-05 23:14:34 +08:00
|
|
|
class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<16> BD1;
|
|
|
|
bits<16> BD2;
|
|
|
|
|
|
|
|
let Inst{47-32} = op;
|
|
|
|
let Inst{31-16} = BD1;
|
|
|
|
let Inst{15-0} = BD2;
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<16> BD1;
|
|
|
|
bits<16> BD2;
|
|
|
|
bits<4> R3;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{11-4};
|
|
|
|
let Inst{39-36} = R3;
|
|
|
|
let Inst{35-32} = op{3-0};
|
|
|
|
let Inst{31-16} = BD1;
|
|
|
|
let Inst{15-0} = BD2;
|
|
|
|
}
|
|
|
|
|
[SystemZ] Support transactional execution on zEC12
The zEC12 provides the transactional-execution facility. This is exposed
to users via a set of builtin routines on other compilers. This patch
adds LLVM support to enable those builtins. In partciular, the patch:
- adds the transactional-execution and processor-assist facilities
- adds MC support for all instructions provided by those facilities
- adds LLVM intrinsics for those instructions and hooks them up for CodeGen
- adds CodeGen support to optimize CC return value checking
Since this is first use of target-specific intrinsics on the platform,
the patch creates the include/llvm/IR/IntrinsicsSystemZ.td file and
hooks it up in Intrinsics.td. I've also changed Triple::getArchTypePrefix
to return "s390" instead of "systemz", since the naming convention for
GCC intrinsics uses "s390" on the platform, and it neemed more straight-
forward to use the same convention for LLVM IR intrinsics.
An associated clang patch makes the intrinsics (and command line switches)
available at the source-language level.
For reference, the transactional-execution instructions are documented
in the z/Architecture Principles of Operation for the zEC12:
http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf
The associated builtins are documented in the GCC manual:
http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html
Index: llvm-head/lib/Target/SystemZ/SystemZOperators.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZOperators.td
+++ llvm-head/lib/Target/SystemZ/SystemZOperators.td
@@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic : SDTypeProf
def SDT_ZPrefetch : SDTypeProfile<0, 2,
[SDTCisVT<0, i32>,
SDTCisPtrTy<1>]>;
+def SDT_ZTBegin : SDTypeProfile<0, 2,
+ [SDTCisPtrTy<0>,
+ SDTCisVT<1, i32>]>;
//===----------------------------------------------------------------------===//
// Node definitions
@@ -180,6 +183,15 @@ def z_prefetch : SDNode<"System
[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
SDNPMemOperand]>;
+def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
+ [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+ SDNPSideEffect]>;
+def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
+ [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+ SDNPSideEffect]>;
+def z_tend : SDNode<"SystemZISD::TEND", SDTNone,
+ [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
+
//===----------------------------------------------------------------------===//
// Pattern fragments
//===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrFormats.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag i
let Inst{15-0} = BD2;
}
+class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<4, outs, ins, asmstr, pattern> {
+ field bits<32> Inst;
+ field bits<32> SoftFail = 0;
+
+ bits<16> BD2;
+
+ let Inst{31-16} = op;
+ let Inst{15-0} = BD2;
+}
+
//===----------------------------------------------------------------------===//
// Instruction definitions with semantics
//===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrInfo.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1362,6 +1362,60 @@ let Defs = [CC] in {
}
//===----------------------------------------------------------------------===//
+// Transactional execution
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureTransactionalExecution] in {
+ // Transaction Begin
+ let hasSideEffects = 1, mayStore = 1,
+ usesCustomInserter = 1, Defs = [CC] in {
+ def TBEGIN : InstSIL<0xE560,
+ (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+ "tbegin\t$BD1, $I2",
+ [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
+ def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+ [(z_tbegin_nofloat bdaddr12only:$BD1,
+ imm32zx16:$I2)]>;
+ def TBEGINC : InstSIL<0xE561,
+ (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+ "tbeginc\t$BD1, $I2",
+ [(int_s390_tbeginc bdaddr12only:$BD1,
+ imm32zx16:$I2)]>;
+ }
+
+ // Transaction End
+ let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
+ def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
+
+ // Transaction Abort
+ let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
+ def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
+ "tabort\t$BD2",
+ [(int_s390_tabort bdaddr12only:$BD2)]>;
+
+ // Nontransactional Store
+ let hasSideEffects = 1 in
+ def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
+
+ // Extract Transaction Nesting Depth
+ let hasSideEffects = 1 in
+ def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
+}
+
+//===----------------------------------------------------------------------===//
+// Processor assist
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureProcessorAssist] in {
+ let hasSideEffects = 1, R4 = 0 in
+ def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
+ "ppa\t$R1, $R2, $R3", []>;
+ def : Pat<(int_s390_ppa_txassist GR32:$src),
+ (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
+ 0, 1)>;
+}
+
+//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZProcessors.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZProcessors.td
+++ llvm-head/lib/Target/SystemZ/SystemZProcessors.td
@@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : Sys
"Assume that the miscellaneous-extensions facility is installed"
>;
+def FeatureTransactionalExecution : SystemZFeature<
+ "transactional-execution", "TransactionalExecution",
+ "Assume that the transactional-execution facility is installed"
+>;
+
+def FeatureProcessorAssist : SystemZFeature<
+ "processor-assist", "ProcessorAssist",
+ "Assume that the processor-assist facility is installed"
+>;
+
def : Processor<"generic", NoItineraries, []>;
def : Processor<"z10", NoItineraries, []>;
def : Processor<"z196", NoItineraries,
@@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries,
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
FeatureFPExtension, FeaturePopulationCount,
FeatureFastSerialization, FeatureInterlockedAccess1,
- FeatureMiscellaneousExtensions]>;
+ FeatureMiscellaneousExtensions,
+ FeatureTransactionalExecution, FeatureProcessorAssist]>;
Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const
HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
HasPopulationCount(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
+ HasTransactionalExecution(false), HasProcessorAssist(false),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {}
Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.h
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
@@ -42,6 +42,8 @@ protected:
bool HasFastSerialization;
bool HasInterlockedAccess1;
bool HasMiscellaneousExtensions;
+ bool HasTransactionalExecution;
+ bool HasProcessorAssist;
private:
Triple TargetTriple;
@@ -102,6 +104,12 @@ public:
return HasMiscellaneousExtensions;
}
+ // Return true if the target has the transactional-execution facility.
+ bool hasTransactionalExecution() const { return HasTransactionalExecution; }
+
+ // Return true if the target has the processor-assist facility.
+ bool hasProcessorAssist() const { return HasProcessorAssist; }
+
// Return true if GV can be accessed using LARL for reloc model RM
// and code model CM.
bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
Index: llvm-head/lib/Support/Triple.cpp
===================================================================
--- llvm-head.orig/lib/Support/Triple.cpp
+++ llvm-head/lib/Support/Triple.cpp
@@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(Ar
case sparcv9:
case sparc: return "sparc";
- case systemz: return "systemz";
+ case systemz: return "s390";
case x86:
case x86_64: return "x86";
Index: llvm-head/include/llvm/IR/Intrinsics.td
===================================================================
--- llvm-head.orig/include/llvm/IR/Intrinsics.td
+++ llvm-head/include/llvm/IR/Intrinsics.td
@@ -634,3 +634,4 @@ include "llvm/IR/IntrinsicsNVVM.td"
include "llvm/IR/IntrinsicsMips.td"
include "llvm/IR/IntrinsicsR600.td"
include "llvm/IR/IntrinsicsBPF.td"
+include "llvm/IR/IntrinsicsSystemZ.td"
Index: llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
===================================================================
--- /dev/null
+++ llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
@@ -0,0 +1,46 @@
+//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the SystemZ-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// Transactional-execution intrinsics
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "s390" in {
+ def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoDuplicate]>;
+
+ def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoDuplicate]>;
+
+ def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrNoDuplicate]>;
+
+ def int_s390_tabort : Intrinsic<[], [llvm_i64_ty],
+ [IntrNoReturn, Throws]>;
+
+ def int_s390_tend : GCCBuiltin<"__builtin_tend">,
+ Intrinsic<[llvm_i32_ty], []>;
+
+ def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">,
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
+
+ def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty],
+ [IntrReadWriteArgMem]>;
+
+ def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">,
+ Intrinsic<[], [llvm_i32_ty]>;
+}
+
Index: llvm-head/lib/Target/SystemZ/SystemZ.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZ.h
+++ llvm-head/lib/Target/SystemZ/SystemZ.h
@@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0 = C
const unsigned CCMASK_TM_MSB_1 = CCMASK_2 | CCMASK_3;
const unsigned CCMASK_TM = CCMASK_ANY;
+// Condition-code mask assignments for TRANSACTION_BEGIN.
+const unsigned CCMASK_TBEGIN_STARTED = CCMASK_0;
+const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1;
+const unsigned CCMASK_TBEGIN_TRANSIENT = CCMASK_2;
+const unsigned CCMASK_TBEGIN_PERSISTENT = CCMASK_3;
+const unsigned CCMASK_TBEGIN = CCMASK_ANY;
+
+// Condition-code mask assignments for TRANSACTION_END.
+const unsigned CCMASK_TEND_TX = CCMASK_0;
+const unsigned CCMASK_TEND_NOTX = CCMASK_2;
+const unsigned CCMASK_TEND = CCMASK_TEND_TX | CCMASK_TEND_NOTX;
+
// The position of the low CC bit in an IPM result.
const unsigned IPM_CC = 28;
Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.h
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
@@ -146,6 +146,15 @@ enum {
// Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
SERIALIZE,
+ // Transaction begin. The first operand is the chain, the second
+ // the TDB pointer, and the third the immediate control field.
+ // Returns chain and glue.
+ TBEGIN,
+ TBEGIN_NOFLOAT,
+
+ // Transaction end. Just the chain operand. Returns chain and glue.
+ TEND,
+
// Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
// ATOMIC_LOAD_<op>.
//
@@ -318,6 +327,7 @@ private:
SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
// If the last instruction before MBBI in MBB was some form of COMPARE,
// try to replace it with a COMPARE AND BRANCH just before MBBI.
@@ -355,6 +365,10 @@ private:
MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
MachineBasicBlock *BB,
unsigned Opcode) const;
+ MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
+ MachineBasicBlock *MBB,
+ unsigned Opcode,
+ bool NoFloat) const;
};
} // end namespace llvm
Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -20,6 +20,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/IR/Intrinsics.h"
#include <cctype>
using namespace llvm;
@@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowe
// Codes for which we want to perform some z-specific combinations.
setTargetDAGCombine(ISD::SIGN_EXTEND);
+ // Handle intrinsics.
+ setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
+
// We want to use MVC in preference to even a single load/store pair.
MaxStoresPerMemcpy = 0;
MaxStoresPerMemcpyOptSize = 0;
@@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chai
return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
}
+// Return true if Op is an intrinsic node with chain that returns the CC value
+// as its only (other) argument. Provide the associated SystemZISD opcode and
+// the mask of valid CC values if so.
+static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
+ unsigned &CCValid) {
+ unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+ switch (Id) {
+ case Intrinsic::s390_tbegin:
+ Opcode = SystemZISD::TBEGIN;
+ CCValid = SystemZ::CCMASK_TBEGIN;
+ return true;
+
+ case Intrinsic::s390_tbegin_nofloat:
+ Opcode = SystemZISD::TBEGIN_NOFLOAT;
+ CCValid = SystemZ::CCMASK_TBEGIN;
+ return true;
+
+ case Intrinsic::s390_tend:
+ Opcode = SystemZISD::TEND;
+ CCValid = SystemZ::CCMASK_TEND;
+ return true;
+
+ default:
+ return false;
+ }
+}
+
+// Emit an intrinsic with chain with a glued value instead of its CC result.
+static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
+ unsigned Opcode) {
+ // Copy all operands except the intrinsic ID.
+ unsigned NumOps = Op.getNumOperands();
+ SmallVector<SDValue, 6> Ops;
+ Ops.reserve(NumOps - 1);
+ Ops.push_back(Op.getOperand(0));
+ for (unsigned I = 2; I < NumOps; ++I)
+ Ops.push_back(Op.getOperand(I));
+
+ assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+ SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
+ SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
+ SDValue OldChain = SDValue(Op.getNode(), 1);
+ SDValue NewChain = SDValue(Intr.getNode(), 0);
+ DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
+ return Intr;
+}
+
// CC is a comparison that will be implemented using an integer or
// floating-point comparison. Return the condition code mask for
// a branch on true. In the integer case, CCMASK_CMP_UO is set for
@@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(Selec
C.CCMask = NewCCMask;
}
+// Return a Comparison that tests the condition-code result of intrinsic
+// node Call against constant integer CC using comparison code Cond.
+// Opcode is the opcode of the SystemZISD operation for the intrinsic
+// and CCValid is the set of possible condition-code results.
+static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
+ SDValue Call, unsigned CCValid, uint64_t CC,
+ ISD::CondCode Cond) {
+ Comparison C(Call, SDValue());
+ C.Opcode = Opcode;
+ C.CCValid = CCValid;
+ if (Cond == ISD::SETEQ)
+ // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
+ C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
+ else if (Cond == ISD::SETNE)
+ // ...and the inverse of that.
+ C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
+ else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
+ // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
+ // always true for CC>3.
+ C.CCMask = CC < 4 ? -1 << (4 - CC) : -1;
+ else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
+ // ...and the inverse of that.
+ C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0;
+ else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
+ // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
+ // always true for CC>3.
+ C.CCMask = CC < 4 ? -1 << (3 - CC) : -1;
+ else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
+ // ...and the inverse of that.
+ C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0;
+ else
+ llvm_unreachable("Unexpected integer comparison type");
+ C.CCMask &= CCValid;
+ return C;
+}
+
// Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
ISD::CondCode Cond) {
+ if (CmpOp1.getOpcode() == ISD::Constant) {
+ uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
+ unsigned Opcode, CCValid;
+ if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
+ CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
+ isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
+ return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
+ }
Comparison C(CmpOp0, CmpOp1);
C.CCMask = CCMaskForCondCode(Cond);
if (C.Op0.getValueType().isFloatingPoint()) {
@@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &D
// Emit the comparison instruction described by C.
static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
+ if (!C.Op1.getNode()) {
+ SDValue Op;
+ switch (C.Op0.getOpcode()) {
+ case ISD::INTRINSIC_W_CHAIN:
+ Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
+ break;
+ default:
+ llvm_unreachable("Invalid comparison operands");
+ }
+ return SDValue(Op.getNode(), Op->getNumValues() - 1);
+ }
if (C.Opcode == SystemZISD::ICMP)
return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
DAG.getConstant(C.ICmpType, MVT::i32));
@@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETC
}
SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
- SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue CmpOp0 = Op.getOperand(2);
SDValue CmpOp1 = Op.getOperand(3);
@@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_C
Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
SDValue Glue = emitCmp(DAG, DL, C);
return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
- Chain, DAG.getConstant(C.CCValid, MVT::i32),
+ Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),
DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
}
@@ -2561,6 +2666,30 @@ SDValue SystemZTargetLowering::lowerPREF
Node->getMemoryVT(), Node->getMemOperand());
}
+// Return an i32 that contains the value of CC immediately after After,
+// whose final operand must be MVT::Glue.
+static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
+ SDValue Glue = SDValue(After, After->getNumValues() - 1);
+ SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);
+ return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
+ DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
+}
+
+SDValue
+SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
+ SelectionDAG &DAG) const {
+ unsigned Opcode, CCValid;
+ if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
+ assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+ SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
+ SDValue CC = getCCResult(DAG, Glued.getNode());
+ DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
+ return SDValue();
+ }
+
+ return SDValue();
+}
+
SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
@@ -2634,6 +2763,8 @@ SDValue SystemZTargetLowering::LowerOper
return lowerSTACKRESTORE(Op, DAG);
case ISD::PREFETCH:
return lowerPREFETCH(Op, DAG);
+ case ISD::INTRINSIC_W_CHAIN:
+ return lowerINTRINSIC_W_CHAIN(Op, DAG);
default:
llvm_unreachable("Unexpected node to lower");
}
@@ -2674,6 +2805,9 @@ const char *SystemZTargetLowering::getTa
OPCODE(SEARCH_STRING);
OPCODE(IPM);
OPCODE(SERIALIZE);
+ OPCODE(TBEGIN);
+ OPCODE(TBEGIN_NOFLOAT);
+ OPCODE(TEND);
OPCODE(ATOMIC_SWAPW);
OPCODE(ATOMIC_LOADW_ADD);
OPCODE(ATOMIC_LOADW_SUB);
@@ -3501,6 +3635,50 @@ SystemZTargetLowering::emitStringWrapper
return DoneMBB;
}
+// Update TBEGIN instruction with final opcode and register clobbers.
+MachineBasicBlock *
+SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
+ MachineBasicBlock *MBB,
+ unsigned Opcode,
+ bool NoFloat) const {
+ MachineFunction &MF = *MBB->getParent();
+ const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
+ const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
+
+ // Update opcode.
+ MI->setDesc(TII->get(Opcode));
+
+ // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
+ // Make sure to add the corresponding GRSM bits if they are missing.
+ uint64_t Control = MI->getOperand(2).getImm();
+ static const unsigned GPRControlBit[16] = {
+ 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
+ 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
+ };
+ Control |= GPRControlBit[15];
+ if (TFI->hasFP(MF))
+ Control |= GPRControlBit[11];
+ MI->getOperand(2).setImm(Control);
+
+ // Add GPR clobbers.
+ for (int I = 0; I < 16; I++) {
+ if ((Control & GPRControlBit[I]) == 0) {
+ unsigned Reg = SystemZMC::GR64Regs[I];
+ MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+ }
+ }
+
+ // Add FPR clobbers.
+ if (!NoFloat && (Control & 4) != 0) {
+ for (int I = 0; I < 16; I++) {
+ unsigned Reg = SystemZMC::FP64Regs[I];
+ MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+ }
+ }
+
+ return MBB;
+}
+
MachineBasicBlock *SystemZTargetLowering::
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
switch (MI->getOpcode()) {
@@ -3742,6 +3920,12 @@ EmitInstrWithCustomInserter(MachineInstr
return emitStringWrapper(MI, MBB, SystemZ::MVST);
case SystemZ::SRSTLoop:
return emitStringWrapper(MI, MBB, SystemZ::SRST);
+ case SystemZ::TBEGIN:
+ return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
+ case SystemZ::TBEGIN_nofloat:
+ return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
+ case SystemZ::TBEGINC:
+ return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
default:
llvm_unreachable("Unexpected instr type to insert");
}
Index: llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
===================================================================
--- /dev/null
+++ llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
@@ -0,0 +1,352 @@
+; Test transactional-execution intrinsics.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
+
+declare i32 @llvm.s390.tbegin(i8 *, i32)
+declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
+declare void @llvm.s390.tbeginc(i8 *, i32)
+declare i32 @llvm.s390.tend()
+declare void @llvm.s390.tabort(i64)
+declare void @llvm.s390.ntstg(i64, i64 *)
+declare i32 @llvm.s390.etnd()
+declare void @llvm.s390.ppa.txassist(i32)
+
+; TBEGIN.
+define void @test_tbegin() {
+; CHECK-LABEL: test_tbegin:
+; CHECK-NOT: stmg
+; CHECK: std %f8,
+; CHECK: std %f9,
+; CHECK: std %f10,
+; CHECK: std %f11,
+; CHECK: std %f12,
+; CHECK: std %f13,
+; CHECK: std %f14,
+; CHECK: std %f15,
+; CHECK: tbegin 0, 65292
+; CHECK: ld %f8,
+; CHECK: ld %f9,
+; CHECK: ld %f10,
+; CHECK: ld %f11,
+; CHECK: ld %f12,
+; CHECK: ld %f13,
+; CHECK: ld %f14,
+; CHECK: ld %f15,
+; CHECK: br %r14
+ call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
+ ret void
+}
+
+; TBEGIN (nofloat).
+define void @test_tbegin_nofloat1() {
+; CHECK-LABEL: test_tbegin_nofloat1:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: br %r14
+ call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+ ret void
+}
+
+; TBEGIN (nofloat) with integer CC return value.
+define i32 @test_tbegin_nofloat2() {
+; CHECK-LABEL: test_tbegin_nofloat2:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+ %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+ ret i32 %res
+}
+
+; TBEGIN (nofloat) with implicit CC check.
+define void @test_tbegin_nofloat3(i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat3:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: jnh {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+ %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+ %cmp = icmp eq i32 %res, 2
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i32 0, i32* %ptr, align 4
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; TBEGIN (nofloat) with dual CC use.
+define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat4:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2, {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+ %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+ %cmp = icmp eq i32 %res, 2
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i32 0, i32* %ptr, align 4
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret i32 %res
+}
+
+; TBEGIN (nofloat) with register.
+define void @test_tbegin_nofloat5(i8 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat5:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0(%r2), 65292
+; CHECK: br %r14
+ call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
+ ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0x0f00.
+define void @test_tbegin_nofloat6() {
+; CHECK-LABEL: test_tbegin_nofloat6:
+; CHECK: stmg %r6, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 3840
+; CHECK: br %r14
+ call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
+ ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xf100.
+define void @test_tbegin_nofloat7() {
+; CHECK-LABEL: test_tbegin_nofloat7:
+; CHECK: stmg %r8, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 61696
+; CHECK: br %r14
+ call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
+ ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
+define void @test_tbegin_nofloat8() {
+; CHECK-LABEL: test_tbegin_nofloat8:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+ call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
+ ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
+define void @test_tbegin_nofloat9() {
+; CHECK-LABEL: test_tbegin_nofloat9:
+; CHECK: stmg %r10, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 64256
+; CHECK: br %r14
+ call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+ ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
+define void @test_tbegin_nofloat10(i64 %n) {
+; CHECK-LABEL: test_tbegin_nofloat10:
+; CHECK: stmg %r11, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+ %buf = alloca i8, i64 %n
+ call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+ ret void
+}
+
+; TBEGINC.
+define void @test_tbeginc() {
+; CHECK-LABEL: test_tbeginc:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbeginc 0, 65288
+; CHECK: br %r14
+ call void @llvm.s390.tbeginc(i8 *null, i32 65288)
+ ret void
+}
+
+; TEND with integer CC return value.
+define i32 @test_tend1() {
+; CHECK-LABEL: test_tend1:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+ %res = call i32 @llvm.s390.tend()
+ ret i32 %res
+}
+
+; TEND with implicit CC check.
+define void @test_tend3(i32 *%ptr) {
+; CHECK-LABEL: test_tend3:
+; CHECK: tend
+; CHECK: je {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+ %res = call i32 @llvm.s390.tend()
+ %cmp = icmp eq i32 %res, 2
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i32 0, i32* %ptr, align 4
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; TEND with dual CC use.
+define i32 @test_tend2(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tend2:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2, {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+ %res = call i32 @llvm.s390.tend()
+ %cmp = icmp eq i32 %res, 2
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i32 0, i32* %ptr, align 4
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret i32 %res
+}
+
+; TABORT with register only.
+define void @test_tabort1(i64 %val) {
+; CHECK-LABEL: test_tabort1:
+; CHECK: tabort 0(%r2)
+; CHECK: br %r14
+ call void @llvm.s390.tabort(i64 %val)
+ ret void
+}
+
+; TABORT with immediate only.
+define void @test_tabort2(i64 %val) {
+; CHECK-LABEL: test_tabort2:
+; CHECK: tabort 1234
+; CHECK: br %r14
+ call void @llvm.s390.tabort(i64 1234)
+ ret void
+}
+
+; TABORT with register + immediate.
+define void @test_tabort3(i64 %val) {
+; CHECK-LABEL: test_tabort3:
+; CHECK: tabort 1234(%r2)
+; CHECK: br %r14
+ %sum = add i64 %val, 1234
+ call void @llvm.s390.tabort(i64 %sum)
+ ret void
+}
+
+; TABORT with out-of-range immediate.
+define void @test_tabort4(i64 %val) {
+; CHECK-LABEL: test_tabort4:
+; CHECK: tabort 0({{%r[1-5]}})
+; CHECK: br %r14
+ call void @llvm.s390.tabort(i64 4096)
+ ret void
+}
+
+; NTSTG with base pointer only.
+define void @test_ntstg1(i64 *%ptr, i64 %val) {
+; CHECK-LABEL: test_ntstg1:
+; CHECK: ntstg %r3, 0(%r2)
+; CHECK: br %r14
+ call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+ ret void
+}
+
+; NTSTG with base and index.
+; Check that VSTL doesn't allow an index.
+define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
+; CHECK-LABEL: test_ntstg2:
+; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
+; CHECK: ntstg %r4, 0([[REG]],%r2)
+; CHECK: br %r14
+ %ptr = getelementptr i64, i64 *%base, i64 %index
+ call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+ ret void
+}
+
+; NTSTG with the highest in-range displacement.
+define void @test_ntstg3(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg3:
+; CHECK: ntstg %r3, 524280(%r2)
+; CHECK: br %r14
+ %ptr = getelementptr i64, i64 *%base, i64 65535
+ call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+ ret void
+}
+
+; NTSTG with an out-of-range positive displacement.
+define void @test_ntstg4(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg4:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+ %ptr = getelementptr i64, i64 *%base, i64 65536
+ call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+ ret void
+}
+
+; NTSTG with the lowest in-range displacement.
+define void @test_ntstg5(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg5:
+; CHECK: ntstg %r3, -524288(%r2)
+; CHECK: br %r14
+ %ptr = getelementptr i64, i64 *%base, i64 -65536
+ call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+ ret void
+}
+
+; NTSTG with an out-of-range negative displacement.
+define void @test_ntstg6(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg6:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+ %ptr = getelementptr i64, i64 *%base, i64 -65537
+ call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+ ret void
+}
+
+; ETND.
+define i32 @test_etnd() {
+; CHECK-LABEL: test_etnd:
+; CHECK: etnd %r2
+; CHECK: br %r14
+ %res = call i32 @llvm.s390.etnd()
+ ret i32 %res
+}
+
+; PPA (Transaction-Abort Assist)
+define void @test_ppa_txassist(i32 %val) {
+; CHECK-LABEL: test_ppa_txassist:
+; CHECK: ppa %r2, 0, 1
+; CHECK: br %r14
+ call void @llvm.s390.ppa.txassist(i32 %val)
+ ret void
+}
+
Index: llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
@@ -3,6 +3,22 @@
# RUN: FileCheck < %t %s
#CHECK: error: invalid operand
+#CHECK: ntstg %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ntstg %r0, 524288
+
+ ntstg %r0, -524289
+ ntstg %r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: ppa %r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: ppa %r0, %r0, 16
+
+ ppa %r0, %r0, -1
+ ppa %r0, %r0, 16
+
+#CHECK: error: invalid operand
#CHECK: risbgn %r0,%r0,0,0,-1
#CHECK: error: invalid operand
#CHECK: risbgn %r0,%r0,0,0,64
@@ -22,3 +38,47 @@
risbgn %r0,%r0,-1,0,0
risbgn %r0,%r0,256,0,0
+#CHECK: error: invalid operand
+#CHECK: tabort -1
+#CHECK: error: invalid operand
+#CHECK: tabort 4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tabort 0(%r1,%r2)
+
+ tabort -1
+ tabort 4096
+ tabort 0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: tbegin -1, 0
+#CHECK: error: invalid operand
+#CHECK: tbegin 4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbegin 0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbegin 0, -1
+#CHECK: error: invalid operand
+#CHECK: tbegin 0, 65536
+
+ tbegin -1, 0
+ tbegin 4096, 0
+ tbegin 0(%r1,%r2), 0
+ tbegin 0, -1
+ tbegin 0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: tbeginc -1, 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc 4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbeginc 0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc 0, -1
+#CHECK: error: invalid operand
+#CHECK: tbeginc 0, 65536
+
+ tbeginc -1, 0
+ tbeginc 4096, 0
+ tbeginc 0(%r1,%r2), 0
+ tbeginc 0, -1
+ tbeginc 0, 65536
Index: llvm-head/test/MC/SystemZ/insn-good-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-good-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-good-zEC12.s
@@ -1,6 +1,48 @@
# For zEC12 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s
+#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00]
+#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0]
+#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70]
+
+ etnd %r0
+ etnd %r15
+ etnd %r7
+
+#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
+#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
+#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25]
+#CHECK: ntstg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25]
+#CHECK: ntstg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25]
+#CHECK: ntstg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25]
+#CHECK: ntstg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25]
+
+ ntstg %r0, -524288
+ ntstg %r0, -1
+ ntstg %r0, 0
+ ntstg %r0, 1
+ ntstg %r0, 524287
+ ntstg %r0, 0(%r1)
+ ntstg %r0, 0(%r15)
+ ntstg %r0, 524287(%r1,%r15)
+ ntstg %r0, 524287(%r15,%r1)
+ ntstg %r15, 0
+
+#CHECK: ppa %r0, %r0, 0 # encoding: [0xb2,0xe8,0x00,0x00]
+#CHECK: ppa %r0, %r0, 15 # encoding: [0xb2,0xe8,0xf0,0x00]
+#CHECK: ppa %r0, %r15, 0 # encoding: [0xb2,0xe8,0x00,0x0f]
+#CHECK: ppa %r4, %r6, 7 # encoding: [0xb2,0xe8,0x70,0x46]
+#CHECK: ppa %r15, %r0, 0 # encoding: [0xb2,0xe8,0x00,0xf0]
+
+ ppa %r0, %r0, 0
+ ppa %r0, %r0, 15
+ ppa %r0, %r15, 0
+ ppa %r4, %r6, 7
+ ppa %r15, %r0, 0
+
#CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
#CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
@@ -17,3 +59,68 @@
risbgn %r15,%r0,0,0,0
risbgn %r4,%r5,6,7,8
+#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00]
+#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00]
+#CHECK: tabort 0(%r15) # encoding: [0xb2,0xfc,0xf0,0x00]
+#CHECK: tabort 4095 # encoding: [0xb2,0xfc,0x0f,0xff]
+#CHECK: tabort 4095(%r1) # encoding: [0xb2,0xfc,0x1f,0xff]
+#CHECK: tabort 4095(%r15) # encoding: [0xb2,0xfc,0xff,0xff]
+
+ tabort 0
+ tabort 0(%r1)
+ tabort 0(%r15)
+ tabort 4095
+ tabort 4095(%r1)
+ tabort 4095(%r15)
+
+#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin 4095, 0 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00]
+#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin 0, 1 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01]
+#CHECK: tbegin 0, 32767 # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff]
+#CHECK: tbegin 0, 32768 # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00]
+#CHECK: tbegin 0, 65535 # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff]
+#CHECK: tbegin 0(%r1), 42 # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a]
+#CHECK: tbegin 0(%r15), 42 # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a]
+#CHECK: tbegin 4095(%r1), 42 # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a]
+#CHECK: tbegin 4095(%r15), 42 # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a]
+
+ tbegin 0, 0
+ tbegin 4095, 0
+ tbegin 0, 0
+ tbegin 0, 1
+ tbegin 0, 32767
+ tbegin 0, 32768
+ tbegin 0, 65535
+ tbegin 0(%r1), 42
+ tbegin 0(%r15), 42
+ tbegin 4095(%r1), 42
+ tbegin 4095(%r15), 42
+
+#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc 4095, 0 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00]
+#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc 0, 1 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01]
+#CHECK: tbeginc 0, 32767 # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff]
+#CHECK: tbeginc 0, 32768 # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00]
+#CHECK: tbeginc 0, 65535 # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff]
+#CHECK: tbeginc 0(%r1), 42 # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a]
+#CHECK: tbeginc 0(%r15), 42 # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a]
+#CHECK: tbeginc 4095(%r1), 42 # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a]
+#CHECK: tbeginc 4095(%r15), 42 # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a]
+
+ tbeginc 0, 0
+ tbeginc 4095, 0
+ tbeginc 0, 0
+ tbeginc 0, 1
+ tbeginc 0, 32767
+ tbeginc 0, 32768
+ tbeginc 0, 65535
+ tbeginc 0(%r1), 42
+ tbeginc 0(%r15), 42
+ tbeginc 4095(%r1), 42
+ tbeginc 4095(%r15), 42
+
+#CHECK: tend # encoding: [0xb2,0xf8,0x00,0x00]
+
+ tend
Index: llvm-head/test/MC/SystemZ/insn-bad-z196.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-z196.s
+++ llvm-head/test/MC/SystemZ/insn-bad-z196.s
@@ -244,6 +244,11 @@
cxlgbr %f0, 16, %r0, 0
cxlgbr %f2, 0, %r0, 0
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: etnd %r7
+
+ etnd %r7
+
#CHECK: error: invalid operand
#CHECK: fidbra %f0, 0, %f0, -1
#CHECK: error: invalid operand
@@ -546,6 +551,16 @@
locr %r0,%r0,-1
locr %r0,%r0,16
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: ntstg %r0, 524287(%r1,%r15)
+
+ ntstg %r0, 524287(%r1,%r15)
+
+#CHECK: error: {{(instruction requires: processor-assist)?}}
+#CHECK: ppa %r4, %r6, 7
+
+ ppa %r4, %r6, 7
+
#CHECK: error: {{(instruction requires: miscellaneous-extensions)?}}
#CHECK: risbgn %r1, %r2, 0, 0, 0
@@ -690,3 +705,24 @@
stocg %r0,-524289,1
stocg %r0,524288,1
stocg %r0,0(%r1,%r2),1
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tabort 4095(%r1)
+
+ tabort 4095(%r1)
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbegin 4095(%r1), 42
+
+ tbegin 4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbeginc 4095(%r1), 42
+
+ tbeginc 4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tend
+
+ tend
+
Index: llvm-head/test/MC/Disassembler/SystemZ/insns.txt
===================================================================
--- llvm-head.orig/test/MC/Disassembler/SystemZ/insns.txt
+++ llvm-head/test/MC/Disassembler/SystemZ/insns.txt
@@ -2503,6 +2503,15 @@
# CHECK: ear %r15, %a15
0xb2 0x4f 0x00 0xff
+# CHECK: etnd %r0
+0xb2 0xec 0x00 0x00
+
+# CHECK: etnd %r15
+0xb2 0xec 0x00 0xf0
+
+# CHECK: etnd %r7
+0xb2 0xec 0x00 0x70
+
# CHECK: fidbr %f0, 0, %f0
0xb3 0x5f 0x00 0x00
@@ -6034,6 +6043,36 @@
# CHECK: ny %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x54
+# CHECK: ntstg %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x25
+
+# CHECK: ntstg %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x25
+
+# CHECK: ntstg %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x25
+
+# CHECK: ntstg %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x25
+
# CHECK: oc 0(1), 0
0xd6 0x00 0x00 0x00 0x00 0x00
@@ -6346,6 +6385,21 @@
# CHECK: popcnt %r7, %r8
0xb9 0xe1 0x00 0x78
+# CHECK: ppa %r0, %r0, 0
+0xb2 0xe8 0x00 0x00
+
+# CHECK: ppa %r0, %r0, 15
+0xb2 0xe8 0xf0 0x00
+
+# CHECK: ppa %r0, %r15, 0
+0xb2 0xe8 0x00 0x0f
+
+# CHECK: ppa %r4, %r6, 7
+0xb2 0xe8 0x70 0x46
+
+# CHECK: ppa %r15, %r0, 0
+0xb2 0xe8 0x00 0xf0
+
# CHECK: risbg %r0, %r0, 0, 0, 0
0xec 0x00 0x00 0x00 0x00 0x55
@@ -8062,6 +8116,93 @@
# CHECK: sy %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x5b
+# CHECK: tabort 0
+0xb2 0xfc 0x00 0x00
+
+# CHECK: tabort 0(%r1)
+0xb2 0xfc 0x10 0x00
+
+# CHECK: tabort 0(%r15)
+0xb2 0xfc 0xf0 0x00
+
+# CHECK: tabort 4095
+0xb2 0xfc 0x0f 0xff
+
+# CHECK: tabort 4095(%r1)
+0xb2 0xfc 0x1f 0xff
+
+# CHECK: tabort 4095(%r15)
+0xb2 0xfc 0xff 0xff
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 4095, 0
+0xe5 0x60 0x0f 0xff 0x00 0x00
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 0, 1
+0xe5 0x60 0x00 0x00 0x00 0x01
+
+# CHECK: tbegin 0, 32767
+0xe5 0x60 0x00 0x00 0x7f 0xff
+
+# CHECK: tbegin 0, 32768
+0xe5 0x60 0x00 0x00 0x80 0x00
+
+# CHECK: tbegin 0, 65535
+0xe5 0x60 0x00 0x00 0xff 0xff
+
+# CHECK: tbegin 0(%r1), 42
+0xe5 0x60 0x10 0x00 0x00 0x2a
+
+# CHECK: tbegin 0(%r15), 42
+0xe5 0x60 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbegin 4095(%r1), 42
+0xe5 0x60 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbegin 4095(%r15), 42
+0xe5 0x60 0xff 0xff 0x00 0x2a
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 4095, 0
+0xe5 0x61 0x0f 0xff 0x00 0x00
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 0, 1
+0xe5 0x61 0x00 0x00 0x00 0x01
+
+# CHECK: tbeginc 0, 32767
+0xe5 0x61 0x00 0x00 0x7f 0xff
+
+# CHECK: tbeginc 0, 32768
+0xe5 0x61 0x00 0x00 0x80 0x00
+
+# CHECK: tbeginc 0, 65535
+0xe5 0x61 0x00 0x00 0xff 0xff
+
+# CHECK: tbeginc 0(%r1), 42
+0xe5 0x61 0x10 0x00 0x00 0x2a
+
+# CHECK: tbeginc 0(%r15), 42
+0xe5 0x61 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r1), 42
+0xe5 0x61 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r15), 42
+0xe5 0x61 0xff 0xff 0x00 0x2a
+
+# CHECK: tend
+0xb2 0xf8 0x00 0x00
+
# CHECK: tm 0, 0
0x91 0x00 0x00 0x00
llvm-svn: 233803
2015-04-01 20:51:43 +08:00
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class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<16> BD2;
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let Inst{31-16} = op;
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let Inst{15-0} = BD2;
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}
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2015-05-06 03:23:40 +08:00
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class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<5> V1;
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bits<16> I2;
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bits<4> M3;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = V1{3-0};
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let Inst{35-32} = 0;
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let Inst{31-16} = I2;
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let Inst{15-12} = M3;
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let Inst{11} = V1{4};
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let Inst{10-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<5> V1;
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bits<8> I2;
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bits<8> I3;
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bits<4> M4;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = V1{3-0};
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let Inst{35-32} = 0;
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let Inst{31-24} = I2;
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let Inst{23-16} = I3;
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let Inst{15-12} = M4;
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let Inst{11} = V1{4};
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let Inst{10-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<5> V1;
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bits<5> V3;
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bits<16> I2;
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bits<4> M4;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = V1{3-0};
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let Inst{35-32} = V3{3-0};
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let Inst{31-16} = I2;
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let Inst{15-12} = M4;
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let Inst{11} = V1{4};
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let Inst{10} = V3{4};
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let Inst{9-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<5> V1;
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bits<5> V2;
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bits<5> V3;
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bits<8> I4;
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bits<4> M5;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = V1{3-0};
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let Inst{35-32} = V2{3-0};
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let Inst{31-28} = V3{3-0};
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let Inst{27-24} = 0;
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let Inst{23-16} = I4;
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let Inst{15-12} = M5;
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let Inst{11} = V1{4};
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let Inst{10} = V2{4};
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let Inst{9} = V3{4};
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let Inst{8} = 0;
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let Inst{7-0} = op{7-0};
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}
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class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<5> V1;
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bits<5> V2;
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bits<12> I3;
|
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bits<4> M4;
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bits<4> M5;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = V1{3-0};
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let Inst{35-32} = V2{3-0};
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let Inst{31-20} = I3;
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let Inst{19-16} = M5;
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let Inst{15-12} = M4;
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let Inst{11} = V1{4};
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let Inst{10} = V2{4};
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let Inst{9-8} = 0;
|
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let Inst{7-0} = op{7-0};
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}
|
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|
|
|
|
// Depending on the instruction mnemonic, certain bits may be or-ed into
|
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|
// the M4 value provided as explicit operand. These are passed as m4or.
|
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class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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bits<4> m4or = 0>
|
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
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field bits<48> Inst;
|
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field bits<48> SoftFail = 0;
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bits<5> V1;
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bits<5> V2;
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bits<4> M3;
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bits<4> M4;
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bits<4> M5;
|
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = V1{3-0};
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let Inst{35-32} = V2{3-0};
|
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let Inst{31-24} = 0;
|
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let Inst{23-20} = M5;
|
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let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3});
|
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let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2});
|
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let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1});
|
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let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0});
|
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let Inst{15-12} = M3;
|
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|
let Inst{11} = V1{4};
|
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|
let Inst{10} = V2{4};
|
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|
let Inst{9-8} = 0;
|
|
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|
let Inst{7-0} = op{7-0};
|
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|
|
}
|
|
|
|
|
|
|
|
// Depending on the instruction mnemonic, certain bits may be or-ed into
|
|
|
|
// the M5 value provided as explicit operand. These are passed as m5or.
|
|
|
|
class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
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|
|
bits<4> m5or = 0>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<5> V2;
|
|
|
|
bits<5> V3;
|
|
|
|
bits<4> M4;
|
|
|
|
bits<4> M5;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
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|
|
let Inst{39-36} = V1{3-0};
|
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|
|
let Inst{35-32} = V2{3-0};
|
|
|
|
let Inst{31-28} = V3{3-0};
|
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|
|
let Inst{27-24} = 0;
|
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|
|
let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3});
|
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|
let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2});
|
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|
let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1});
|
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|
let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0});
|
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|
let Inst{19-16} = 0;
|
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|
let Inst{15-12} = M4;
|
|
|
|
let Inst{11} = V1{4};
|
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|
let Inst{10} = V2{4};
|
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|
|
let Inst{9} = V3{4};
|
|
|
|
let Inst{8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<5> V2;
|
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|
|
bits<5> V3;
|
|
|
|
bits<4> M4;
|
|
|
|
bits<4> M5;
|
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|
|
bits<4> M6;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
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|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-32} = V2{3-0};
|
|
|
|
let Inst{31-28} = V3{3-0};
|
|
|
|
let Inst{27-24} = 0;
|
|
|
|
let Inst{23-20} = M6;
|
|
|
|
let Inst{19-16} = M5;
|
|
|
|
let Inst{15-12} = M4;
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10} = V2{4};
|
|
|
|
let Inst{9} = V3{4};
|
|
|
|
let Inst{8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
// Depending on the instruction mnemonic, certain bits may be or-ed into
|
|
|
|
// the M6 value provided as explicit operand. These are passed as m6or.
|
|
|
|
class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
|
|
|
bits<4> m6or = 0>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<5> V2;
|
|
|
|
bits<5> V3;
|
|
|
|
bits<5> V4;
|
|
|
|
bits<4> M5;
|
|
|
|
bits<4> M6;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-32} = V2{3-0};
|
|
|
|
let Inst{31-28} = V3{3-0};
|
|
|
|
let Inst{27-24} = M5;
|
|
|
|
let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3});
|
|
|
|
let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2});
|
|
|
|
let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1});
|
|
|
|
let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0});
|
|
|
|
let Inst{19-16} = 0;
|
|
|
|
let Inst{15-12} = V4{3-0};
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10} = V2{4};
|
|
|
|
let Inst{9} = V3{4};
|
|
|
|
let Inst{8} = V4{4};
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<5> V2;
|
|
|
|
bits<5> V3;
|
|
|
|
bits<5> V4;
|
|
|
|
bits<4> M5;
|
|
|
|
bits<4> M6;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-32} = V2{3-0};
|
|
|
|
let Inst{31-28} = V3{3-0};
|
|
|
|
let Inst{27-24} = M6;
|
|
|
|
let Inst{23-20} = 0;
|
|
|
|
let Inst{19-16} = M5;
|
|
|
|
let Inst{15-12} = V4{3-0};
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10} = V2{4};
|
|
|
|
let Inst{9} = V3{4};
|
|
|
|
let Inst{8} = V4{4};
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<4> R2;
|
|
|
|
bits<4> R3;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-32} = R2;
|
|
|
|
let Inst{31-28} = R3;
|
|
|
|
let Inst{27-12} = 0;
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<16> BD2;
|
|
|
|
bits<5> V3;
|
|
|
|
bits<4> M4;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-32} = V3{3-0};
|
|
|
|
let Inst{31-16} = BD2;
|
|
|
|
let Inst{15-12} = M4;
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10} = V3{4};
|
|
|
|
let Inst{9-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<16> BD2;
|
|
|
|
bits<4> R3;
|
|
|
|
bits<4> M4;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-32} = R3;
|
|
|
|
let Inst{31-16} = BD2;
|
|
|
|
let Inst{15-12} = M4;
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<4> R1;
|
|
|
|
bits<16> BD2;
|
|
|
|
bits<5> V3;
|
|
|
|
bits<4> M4;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = R1;
|
|
|
|
let Inst{35-32} = V3{3-0};
|
|
|
|
let Inst{31-16} = BD2;
|
|
|
|
let Inst{15-12} = M4;
|
|
|
|
let Inst{11} = 0;
|
|
|
|
let Inst{10} = V3{4};
|
|
|
|
let Inst{9-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<21> VBD2;
|
|
|
|
bits<4> M3;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-16} = VBD2{19-0};
|
|
|
|
let Inst{15-12} = M3;
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10} = VBD2{20};
|
|
|
|
let Inst{9-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSystemZ<6, outs, ins, asmstr, pattern> {
|
|
|
|
field bits<48> Inst;
|
|
|
|
field bits<48> SoftFail = 0;
|
|
|
|
|
|
|
|
bits<5> V1;
|
|
|
|
bits<20> XBD2;
|
|
|
|
bits<4> M3;
|
|
|
|
|
|
|
|
let Inst{47-40} = op{15-8};
|
|
|
|
let Inst{39-36} = V1{3-0};
|
|
|
|
let Inst{35-16} = XBD2;
|
|
|
|
let Inst{15-12} = M3;
|
|
|
|
let Inst{11} = V1{4};
|
|
|
|
let Inst{10-8} = 0;
|
|
|
|
let Inst{7-0} = op{7-0};
|
|
|
|
}
|
|
|
|
|
2016-08-08 23:13:08 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Instruction classes for .insn directives
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstE<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<16> enc;
|
|
|
|
|
|
|
|
let Inst = enc;
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRIa<0, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-24} = enc{31-24};
|
|
|
|
let Inst{19-16} = enc{19-16};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRIEd<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRILa<0, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits<48> enc;
|
|
|
|
string type;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{35-32} = enc{35-32};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRIS<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRR<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<16> enc;
|
|
|
|
|
|
|
|
let Inst{15-8} = enc{15-8};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRRE<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-16} = enc{31-16};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:36:31 +08:00
|
|
|
: InstRRFa<0, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-16} = enc{31-16};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRRS<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSa<0, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-24} = enc{31-24};
|
|
|
|
}
|
|
|
|
|
|
|
|
// RSE is like RSY except with a 12 bit displacement (instead of 20).
|
|
|
|
class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSYa<6, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits <48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{31-16} = BD2{15-0};
|
|
|
|
let Inst{15-8} = 0;
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRSI<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-24} = enc{31-24};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSYa<0, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXa<0, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-24} = enc{31-24};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRXE<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let M3 = 0;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstRXF<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXYa<0, outs, ins, asmstr, pattern> {
|
2016-08-08 23:13:08 +08:00
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstS<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-16} = enc{31-16};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSI<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<32> enc;
|
|
|
|
|
|
|
|
let Inst{31-24} = enc{31-24};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSIY<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{7-0} = enc{7-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSIL<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-32} = enc{47-32};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSSd<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSSE<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-32} = enc{47-32};
|
|
|
|
}
|
|
|
|
|
|
|
|
class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
|
|
: InstSSF<0, outs, ins, asmstr, pattern> {
|
|
|
|
bits<48> enc;
|
|
|
|
|
|
|
|
let Inst{47-40} = enc{47-40};
|
|
|
|
let Inst{35-32} = enc{35-32};
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Variants of instructions with condition mask
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// For instructions using a condition mask (e.g. conditional branches,
|
|
|
|
// compare-and-branch instructions, or conditional move instructions),
|
|
|
|
// we generally need to create multiple instruction patterns:
|
|
|
|
//
|
|
|
|
// - One used for code generation, which encodes the condition mask as an
|
|
|
|
// MI operand, but writes out an extended mnemonic for better readability.
|
|
|
|
// - One pattern for the base form of the instruction with an explicit
|
|
|
|
// condition mask (encoded as a plain integer MI operand).
|
|
|
|
// - Specific patterns for each extended mnemonic, where the condition mask
|
|
|
|
// is implied by the pattern name and not otherwise encoded at all.
|
|
|
|
//
|
|
|
|
// We need the latter primarily for the assembler and disassembler, since the
|
|
|
|
// assembler parser is not able to decode part of an instruction mnemonic
|
|
|
|
// into an operand. Thus we provide separate patterns for each mnemonic.
|
|
|
|
//
|
|
|
|
// Note that in some cases there are two different mnemonics for the same
|
|
|
|
// condition mask. In this case we cannot have both instructions available
|
|
|
|
// to the disassembler at the same time since the encodings are not distinct.
|
|
|
|
// Therefore the alternate forms are marked isAsmParserOnly.
|
|
|
|
//
|
|
|
|
// We don't make one of the two names an alias of the other because
|
|
|
|
// we need the custom parsing routines to select the correct register class.
|
|
|
|
//
|
|
|
|
// This section provides helpers for generating the specific forms.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// A class to describe a variant of an instruction with condition mask.
|
|
|
|
class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
|
|
|
|
// The fixed condition mask to use.
|
|
|
|
bits<4> ccmask = ccmaskin;
|
|
|
|
|
|
|
|
// The suffix to use for the extended assembler mnemonic.
|
|
|
|
string suffix = suffixin;
|
|
|
|
|
|
|
|
// Whether this is an alternate that needs to be marked isAsmParserOnly.
|
|
|
|
bit alternate = alternatein;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Condition mask 15 means "always true", which is used to define
|
|
|
|
// unconditional branches as a variant of conditional branches.
|
|
|
|
def CondAlways : CondVariant<15, "", 0>;
|
|
|
|
|
|
|
|
// Condition masks for general instructions that can set all 4 bits.
|
|
|
|
def CondVariantO : CondVariant<1, "o", 0>;
|
|
|
|
def CondVariantH : CondVariant<2, "h", 0>;
|
|
|
|
def CondVariantP : CondVariant<2, "p", 1>;
|
|
|
|
def CondVariantNLE : CondVariant<3, "nle", 0>;
|
|
|
|
def CondVariantL : CondVariant<4, "l", 0>;
|
|
|
|
def CondVariantM : CondVariant<4, "m", 1>;
|
|
|
|
def CondVariantNHE : CondVariant<5, "nhe", 0>;
|
|
|
|
def CondVariantLH : CondVariant<6, "lh", 0>;
|
|
|
|
def CondVariantNE : CondVariant<7, "ne", 0>;
|
|
|
|
def CondVariantNZ : CondVariant<7, "nz", 1>;
|
|
|
|
def CondVariantE : CondVariant<8, "e", 0>;
|
|
|
|
def CondVariantZ : CondVariant<8, "z", 1>;
|
|
|
|
def CondVariantNLH : CondVariant<9, "nlh", 0>;
|
|
|
|
def CondVariantHE : CondVariant<10, "he", 0>;
|
|
|
|
def CondVariantNL : CondVariant<11, "nl", 0>;
|
|
|
|
def CondVariantNM : CondVariant<11, "nm", 1>;
|
|
|
|
def CondVariantLE : CondVariant<12, "le", 0>;
|
|
|
|
def CondVariantNH : CondVariant<13, "nh", 0>;
|
|
|
|
def CondVariantNP : CondVariant<13, "np", 1>;
|
|
|
|
def CondVariantNO : CondVariant<14, "no", 0>;
|
|
|
|
|
|
|
|
// A helper class to look up one of the above by name.
|
|
|
|
class CV<string name>
|
|
|
|
: CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
|
|
|
|
!cast<CondVariant>("CondVariant"#name).suffix,
|
|
|
|
!cast<CondVariant>("CondVariant"#name).alternate>;
|
|
|
|
|
|
|
|
// Condition masks for integer instructions (e.g. compare-and-branch).
|
|
|
|
// This is like the list above, except that condition 3 is not possible
|
|
|
|
// and that the low bit of the mask is therefore always 0. This means
|
|
|
|
// that each condition has two names. Conditions "o" and "no" are not used.
|
|
|
|
def IntCondVariantH : CondVariant<2, "h", 0>;
|
|
|
|
def IntCondVariantNLE : CondVariant<2, "nle", 1>;
|
|
|
|
def IntCondVariantL : CondVariant<4, "l", 0>;
|
|
|
|
def IntCondVariantNHE : CondVariant<4, "nhe", 1>;
|
|
|
|
def IntCondVariantLH : CondVariant<6, "lh", 0>;
|
|
|
|
def IntCondVariantNE : CondVariant<6, "ne", 1>;
|
|
|
|
def IntCondVariantE : CondVariant<8, "e", 0>;
|
|
|
|
def IntCondVariantNLH : CondVariant<8, "nlh", 1>;
|
|
|
|
def IntCondVariantHE : CondVariant<10, "he", 0>;
|
|
|
|
def IntCondVariantNL : CondVariant<10, "nl", 1>;
|
|
|
|
def IntCondVariantLE : CondVariant<12, "le", 0>;
|
|
|
|
def IntCondVariantNH : CondVariant<12, "nh", 1>;
|
|
|
|
|
|
|
|
// A helper class to look up one of the above by name.
|
|
|
|
class ICV<string name>
|
|
|
|
: CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
|
|
|
|
!cast<CondVariant>("IntCondVariant"#name).suffix,
|
|
|
|
!cast<CondVariant>("IntCondVariant"#name).alternate>;
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Instruction definitions with semantics
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
2013-07-25 16:57:02 +08:00
|
|
|
// These classes have the form [Cond]<Category><Format>, where <Format> is one
|
2013-05-07 00:15:19 +08:00
|
|
|
// of the formats defined above and where <Category> describes the inputs
|
2013-07-25 16:57:02 +08:00
|
|
|
// and outputs. "Cond" is used if the instruction is conditional,
|
|
|
|
// in which case the 4-bit condition-code mask is added as a final operand.
|
|
|
|
// <Category> can be one of:
|
2013-05-07 00:15:19 +08:00
|
|
|
//
|
|
|
|
// Inherent:
|
|
|
|
// One register output operand and no input operands.
|
|
|
|
//
|
2016-11-09 02:37:48 +08:00
|
|
|
// StoreInherent:
|
|
|
|
// One address operand. The instruction stores to the address.
|
|
|
|
//
|
|
|
|
// SideEffectInherent:
|
|
|
|
// No input or output operands, but causes some side effect.
|
|
|
|
//
|
2016-11-09 02:30:50 +08:00
|
|
|
// Branch:
|
|
|
|
// One branch target. The instruction branches to the target.
|
|
|
|
//
|
|
|
|
// Call:
|
|
|
|
// One output operand and one branch target. The instruction stores
|
|
|
|
// the return address to the output operand and branches to the target.
|
|
|
|
//
|
|
|
|
// CmpBranch:
|
|
|
|
// Two input operands and one optional branch target. The instruction
|
|
|
|
// compares the two input operands and branches or traps on the result.
|
|
|
|
//
|
2013-08-05 19:07:38 +08:00
|
|
|
// BranchUnary:
|
2016-11-28 21:40:08 +08:00
|
|
|
// One register output operand, one register input operand and one branch
|
|
|
|
// target. The instructions stores a modified form of the source register
|
|
|
|
// in the destination register and branches on the result.
|
2013-08-05 19:07:38 +08:00
|
|
|
//
|
2016-08-05 23:14:34 +08:00
|
|
|
// BranchBinary:
|
|
|
|
// One register output operand, two register input operands and one branch
|
2016-11-28 21:40:08 +08:00
|
|
|
// target. The instructions stores a modified form of one of the source
|
|
|
|
// registers in the destination register and branches on the result.
|
2016-08-05 23:14:34 +08:00
|
|
|
//
|
2013-05-07 00:15:19 +08:00
|
|
|
// LoadMultiple:
|
|
|
|
// One address input operand and two explicit output operands.
|
|
|
|
// The instruction loads a range of registers from the address,
|
|
|
|
// with the explicit operands giving the first and last register
|
|
|
|
// to load. Other loaded registers are added as implicit definitions.
|
|
|
|
//
|
|
|
|
// StoreMultiple:
|
|
|
|
// Two explicit input register operands and an address operand.
|
|
|
|
// The instruction stores a range of registers to the address,
|
|
|
|
// with the explicit operands giving the first and last register
|
|
|
|
// to store. Other stored registers are added as implicit uses.
|
|
|
|
//
|
2015-05-06 03:23:40 +08:00
|
|
|
// StoreLength:
|
|
|
|
// One value operand, one length operand and one address operand.
|
|
|
|
// The instruction stores the value operand to the address but
|
|
|
|
// doesn't write more than the number of bytes specified by the
|
|
|
|
// length operand.
|
|
|
|
//
|
2016-11-09 02:37:48 +08:00
|
|
|
// LoadAddress:
|
|
|
|
// One register output operand and one address operand.
|
|
|
|
//
|
2016-12-03 02:21:53 +08:00
|
|
|
// SideEffectAddress:
|
|
|
|
// One address operand. No output operands, but causes some side effect.
|
|
|
|
//
|
2013-05-07 00:15:19 +08:00
|
|
|
// Unary:
|
2014-07-10 19:29:23 +08:00
|
|
|
// One register output operand and one input operand.
|
2013-05-07 00:15:19 +08:00
|
|
|
//
|
2015-05-06 03:23:40 +08:00
|
|
|
// Store:
|
|
|
|
// One address operand and one other input operand. The instruction
|
|
|
|
// stores to the address.
|
|
|
|
//
|
2016-11-09 02:37:48 +08:00
|
|
|
// SideEffectUnary:
|
|
|
|
// One input operand. No output operands, but causes some side effect.
|
|
|
|
//
|
2013-05-07 00:15:19 +08:00
|
|
|
// Binary:
|
2014-07-10 19:29:23 +08:00
|
|
|
// One register output operand and two input operands.
|
2013-05-07 00:15:19 +08:00
|
|
|
//
|
2015-05-06 03:23:40 +08:00
|
|
|
// StoreBinary:
|
|
|
|
// One address operand and two other input operands. The instruction
|
|
|
|
// stores to the address.
|
|
|
|
//
|
2016-11-09 02:37:48 +08:00
|
|
|
// SideEffectBinary:
|
|
|
|
// Two input operands. No output operands, but causes some side effect.
|
|
|
|
//
|
2013-05-07 00:15:19 +08:00
|
|
|
// Compare:
|
2014-07-10 19:29:23 +08:00
|
|
|
// Two input operands and an implicit CC output operand.
|
2013-05-07 00:15:19 +08:00
|
|
|
//
|
2016-06-29 15:29:07 +08:00
|
|
|
// Test:
|
2017-05-10 20:42:45 +08:00
|
|
|
// One or two input operands and an implicit CC output operand. If
|
|
|
|
// present, the second input operand is an "address" operand used as
|
|
|
|
// a test class mask.
|
2016-06-29 15:29:07 +08:00
|
|
|
//
|
2013-05-07 00:15:19 +08:00
|
|
|
// Ternary:
|
2014-07-10 19:29:23 +08:00
|
|
|
// One register output operand and three input operands.
|
2013-05-07 00:15:19 +08:00
|
|
|
//
|
2016-11-09 02:37:48 +08:00
|
|
|
// SideEffectTernary:
|
|
|
|
// Three input operands. No output operands, but causes some side effect.
|
|
|
|
//
|
2015-05-06 03:23:40 +08:00
|
|
|
// Quaternary:
|
|
|
|
// One register output operand and four input operands.
|
|
|
|
//
|
2013-12-24 23:14:05 +08:00
|
|
|
// LoadAndOp:
|
2014-07-10 19:29:23 +08:00
|
|
|
// One output operand and two input operands, one of which is an address.
|
|
|
|
// The instruction both reads from and writes to the address.
|
2013-12-24 23:14:05 +08:00
|
|
|
//
|
2013-05-07 00:15:19 +08:00
|
|
|
// CmpSwap:
|
2014-07-10 19:29:23 +08:00
|
|
|
// One output operand and three input operands, one of which is an address.
|
|
|
|
// The instruction both reads from and writes to the address.
|
2013-05-07 00:15:19 +08:00
|
|
|
//
|
|
|
|
// RotateSelect:
|
|
|
|
// One output operand and five input operands. The first two operands
|
|
|
|
// are registers and the other three are immediates.
|
|
|
|
//
|
2013-08-23 19:36:42 +08:00
|
|
|
// Prefetch:
|
|
|
|
// One 4-bit immediate operand and one address operand. The immediate
|
|
|
|
// operand is 1 for a load prefetch and 2 for a store prefetch.
|
|
|
|
//
|
2016-11-28 22:01:51 +08:00
|
|
|
// BranchPreload:
|
|
|
|
// One 4-bit immediate operand and two address operands.
|
|
|
|
//
|
2013-05-07 00:15:19 +08:00
|
|
|
// The format determines which input operands are tied to output operands,
|
|
|
|
// and also determines the shape of any address operand.
|
|
|
|
//
|
|
|
|
// Multiclasses of the form <Category><Format>Pair define two instructions,
|
|
|
|
// one with <Category><Format> and one with <Category><Format>Y. The name
|
|
|
|
// of the first instruction has no suffix, the name of the second has
|
|
|
|
// an extra "y".
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
2016-11-09 02:37:48 +08:00
|
|
|
SDPatternOperator operator>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRRE<opcode, (outs cls:$R1), (ins),
|
2013-08-12 18:05:58 +08:00
|
|
|
mnemonic#"\t$R1",
|
2016-11-09 02:37:48 +08:00
|
|
|
[(set cls:$R1, (operator))]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let R2 = 0;
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
|
|
|
|
: InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
|
|
|
|
let I2 = value;
|
|
|
|
let M3 = 0;
|
|
|
|
}
|
|
|
|
|
2016-12-03 02:21:53 +08:00
|
|
|
class StoreInherentS<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator, bits<5> bytes>
|
2016-11-09 02:37:48 +08:00
|
|
|
: InstS<opcode, (outs), (ins bdaddr12only:$BD2),
|
2016-12-03 02:21:53 +08:00
|
|
|
mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
|
2016-11-09 02:37:48 +08:00
|
|
|
let mayStore = 1;
|
2016-12-03 02:21:53 +08:00
|
|
|
let AccessBytes = bytes;
|
2016-11-09 02:37:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class SideEffectInherentE<string mnemonic, bits<16>opcode>
|
2016-12-03 02:19:22 +08:00
|
|
|
: InstE<opcode, (outs), (ins), mnemonic, []>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
|
|
|
class SideEffectInherentS<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator>
|
|
|
|
: InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
|
|
|
|
let BD2 = 0;
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:42:00 +08:00
|
|
|
class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
|
|
|
|
: InstRRE<opcode, (outs), (ins), mnemonic, []> {
|
|
|
|
let R1 = 0;
|
|
|
|
let R2 = 0;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
// Allow an optional TLS marker symbol to generate TLS call relocations.
|
|
|
|
class CallRI<string mnemonic, bits<12> opcode>
|
|
|
|
: InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
|
|
|
|
mnemonic#"\t$R1, $RI2", []>;
|
|
|
|
|
|
|
|
// Allow an optional TLS marker symbol to generate TLS call relocations.
|
|
|
|
class CallRIL<string mnemonic, bits<12> opcode>
|
|
|
|
: InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
|
|
|
|
mnemonic#"\t$R1, $RI2", []>;
|
|
|
|
|
|
|
|
class CallRR<string mnemonic, bits<8> opcode>
|
|
|
|
: InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
|
|
|
|
mnemonic#"\t$R1, $R2", []>;
|
|
|
|
|
|
|
|
class CallRX<string mnemonic, bits<8> opcode>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2", []>;
|
2016-11-09 02:30:50 +08:00
|
|
|
|
|
|
|
class CondBranchRI<string mnemonic, bits<12> opcode,
|
|
|
|
SDPatternOperator operator = null_frag>
|
|
|
|
: InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
|
|
|
|
!subst("#", "${M1}", mnemonic)#"\t$RI2",
|
|
|
|
[(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
|
|
|
|
let CCMaskFirst = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class AsmCondBranchRI<string mnemonic, bits<12> opcode>
|
|
|
|
: InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
|
|
|
|
mnemonic#"\t$M1, $RI2", []>;
|
|
|
|
|
|
|
|
class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
|
|
|
|
SDPatternOperator operator = null_frag>
|
|
|
|
: InstRIc<opcode, (outs), (ins brtarget16:$RI2),
|
|
|
|
!subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M1 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CondBranchRIL<string mnemonic, bits<12> opcode>
|
|
|
|
: InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
|
|
|
|
!subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
|
|
|
|
let CCMaskFirst = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
|
|
|
|
: InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
|
|
|
|
mnemonic#"\t$M1, $RI2", []>;
|
|
|
|
|
|
|
|
class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
|
|
|
|
: InstRILc<opcode, (outs), (ins brtarget32:$RI2),
|
|
|
|
!subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M1 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CondBranchRR<string mnemonic, bits<8> opcode>
|
|
|
|
: InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
|
|
|
|
!subst("#", "${R1}", mnemonic)#"\t$R2", []> {
|
|
|
|
let CCMaskFirst = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class AsmCondBranchRR<string mnemonic, bits<8> opcode>
|
|
|
|
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
|
|
|
|
mnemonic#"\t$R1, $R2", []>;
|
|
|
|
|
|
|
|
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
|
|
|
|
SDPatternOperator operator = null_frag>
|
|
|
|
: InstRR<opcode, (outs), (ins ADDR64:$R2),
|
|
|
|
!subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let R1 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CondBranchRX<string mnemonic, bits<8> opcode>
|
|
|
|
: InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
|
|
|
|
!subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
|
|
|
|
let CCMaskFirst = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class AsmCondBranchRX<string mnemonic, bits<8> opcode>
|
|
|
|
: InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$M1, $XBD2", []>;
|
|
|
|
|
|
|
|
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
|
|
|
|
: InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
|
|
|
|
!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M1 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CmpBranchRIEa<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
|
|
|
|
mnemonic#"$M3\t$R1, $I2", []>;
|
|
|
|
|
|
|
|
class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$R1, $I2, $M3", []>;
|
|
|
|
|
|
|
|
class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $I2", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
|
|
|
|
def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CmpBranchRIEb<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRIEb<opcode, (outs),
|
|
|
|
(ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
|
|
|
|
mnemonic#"$M3\t$R1, $R2, $RI4", []>;
|
|
|
|
|
|
|
|
class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRIEb<opcode, (outs),
|
|
|
|
(ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
|
|
|
|
mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
|
|
|
|
|
|
|
|
class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
|
|
|
|
def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CmpBranchRIEc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIEc<opcode, (outs),
|
|
|
|
(ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
|
|
|
|
mnemonic#"$M3\t$R1, $I2, $RI4", []>;
|
|
|
|
|
|
|
|
class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIEc<opcode, (outs),
|
|
|
|
(ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
|
|
|
|
mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
|
|
|
|
|
|
|
|
class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
|
|
|
|
def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CmpBranchRRFc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
|
|
|
|
mnemonic#"$M3\t$R1, $R2", []>;
|
|
|
|
|
|
|
|
class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$R1, $R2, $M3", []>;
|
|
|
|
|
|
|
|
multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
|
|
|
|
def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $R2", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CmpBranchRRS<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRRS<opcode, (outs),
|
|
|
|
(ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
|
|
|
|
mnemonic#"$M3\t$R1, $R2, $BD4", []>;
|
|
|
|
|
|
|
|
class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRRS<opcode, (outs),
|
|
|
|
(ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
|
|
|
|
mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
|
|
|
|
|
|
|
|
class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CmpBranchRRS<mnemonic, opcode, cls>;
|
|
|
|
def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CmpBranchRIS<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIS<opcode, (outs),
|
|
|
|
(ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
|
|
|
|
mnemonic#"$M3\t$R1, $I2, $BD4", []>;
|
|
|
|
|
|
|
|
class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIS<opcode, (outs),
|
|
|
|
(ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
|
|
|
|
mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
|
|
|
|
|
|
|
|
class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, Immediate imm> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
|
|
|
|
def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
|
|
|
|
}
|
|
|
|
|
2016-11-11 20:48:26 +08:00
|
|
|
class CmpBranchRSYb<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
|
|
|
|
mnemonic#"$M3\t$R1, $BD2", []>;
|
|
|
|
|
|
|
|
class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$R1, $M3, $BD2", []>;
|
|
|
|
|
|
|
|
multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
|
|
|
|
def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $BD2", []> {
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
2013-08-05 19:07:38 +08:00
|
|
|
class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
|
|
|
|
mnemonic##"\t$R1, $RI2", []> {
|
2016-08-05 23:14:34 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
2016-11-28 21:40:08 +08:00
|
|
|
class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
|
|
|
|
: InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
|
|
|
|
mnemonic##"\t$R1, $RI2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
|
|
|
: InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
|
|
|
|
mnemonic##"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
|
|
|
: InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
|
|
|
|
mnemonic##"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
|
|
|
: InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic##"\t$R1, $XBD2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
|
|
|
: InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
|
|
|
|
mnemonic##"\t$R1, $XBD2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
2016-08-05 23:14:34 +08:00
|
|
|
class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
|
|
|
: InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
|
|
|
|
mnemonic##"\t$R1, $R3, $RI2", []> {
|
2013-08-05 19:07:38 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
2016-11-28 21:40:08 +08:00
|
|
|
class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
|
|
|
: InstRIEe<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, cls:$R3, brtarget16:$RI2),
|
|
|
|
mnemonic##"\t$R1, $R3, $RI2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
|
|
|
: InstRSa<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
|
|
|
|
mnemonic##"\t$R1, $R3, $BD2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
|
|
|
: InstRSYa<opcode,
|
|
|
|
(outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
|
|
|
|
mnemonic##"\t$R1, $R3, $BD2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
|
|
|
|
AddressingMode mode = bdaddr12only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
|
|
|
AddressingMode mode = bdaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
|
|
|
|
bits<16> rsyOpcode, RegisterOperand cls> {
|
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
|
|
|
def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
|
|
|
|
let DispSize = "20" in
|
|
|
|
def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
|
|
|
|
mnemonic#"\t$V1, $V3, $BD2", []> {
|
|
|
|
let M4 = 0;
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
|
|
|
|
mnemonic#"\t$R1, $RI2",
|
|
|
|
[(operator cls:$R1, pcrel32:$RI2)]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
|
|
// complex.
|
|
|
|
let AddedComplexity = 7;
|
|
|
|
}
|
|
|
|
|
|
|
|
class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdxaddr12only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(operator cls:$R1, mode:$XBD2)]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayStore = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdxaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(operator cls:$R1, mode:$XBD2)]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayStore = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
2013-07-03 18:10:02 +08:00
|
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
bits<5> bytes> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
2013-07-03 18:10:02 +08:00
|
|
|
def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-07-03 18:10:02 +08:00
|
|
|
def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
|
|
|
|
bdxaddr20pair>;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr, bits<5> bytes, bits<4> type = 0>
|
|
|
|
: InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$V1, $XBD2",
|
|
|
|
[(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
|
|
|
|
let M3 = type;
|
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class StoreLengthVRSb<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator, bits<5> bytes>
|
|
|
|
: InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
|
|
|
|
mnemonic#"\t$V1, $R3, $BD2",
|
|
|
|
[(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
|
|
|
|
let M4 = 0;
|
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
|
|
|
|
AddressingMode mode = bdaddr12only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
|
|
|
AddressingMode mode = bdaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
|
|
|
|
bits<16> rsyOpcode, RegisterOperand cls> {
|
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
|
|
|
def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
|
|
|
|
let DispSize = "20" in
|
|
|
|
def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
|
|
|
|
mnemonic#"\t$V1, $V3, $BD2", []> {
|
|
|
|
let M4 = 0;
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
2013-08-23 19:18:53 +08:00
|
|
|
// StoreSI* instructions are used to store an integer to memory, but the
|
|
|
|
// addresses are more restricted than for normal stores. If we are in the
|
|
|
|
// situation of having to force either the address into a register or the
|
|
|
|
// constant into a register, it's usually better to do the latter.
|
|
|
|
// We therefore match the address in the same way as a normal store and
|
|
|
|
// only use the StoreSI* instruction if the matched address is suitable.
|
2013-05-07 00:15:19 +08:00
|
|
|
class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
2013-08-23 19:18:53 +08:00
|
|
|
Immediate imm>
|
|
|
|
: InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
|
2013-05-14 17:28:21 +08:00
|
|
|
mnemonic#"\t$BD1, $I2",
|
2013-08-23 19:18:53 +08:00
|
|
|
[(operator imm:$I2, mviaddr12pair:$BD1)]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-08-23 19:18:53 +08:00
|
|
|
Immediate imm>
|
|
|
|
: InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
|
2013-05-14 17:28:21 +08:00
|
|
|
mnemonic#"\t$BD1, $I2",
|
2013-08-23 19:18:53 +08:00
|
|
|
[(operator imm:$I2, mviaddr20pair:$BD1)]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
Immediate imm>
|
2013-08-23 19:18:53 +08:00
|
|
|
: InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
|
2013-05-14 17:28:21 +08:00
|
|
|
mnemonic#"\t$BD1, $I2",
|
2013-08-23 19:18:53 +08:00
|
|
|
[(operator imm:$I2, mviaddr12pair:$BD1)]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
|
|
|
|
SDPatternOperator operator, Immediate imm> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic in {
|
|
|
|
let DispSize = "12" in
|
2013-08-23 19:18:53 +08:00
|
|
|
def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-08-23 19:18:53 +08:00
|
|
|
def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class StoreSSE<string mnemonic, bits<16> opcode>
|
|
|
|
: InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
|
|
|
|
mnemonic#"\t$BD1, $BD2", []> {
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
2013-07-25 16:57:02 +08:00
|
|
|
class CondStoreRSY<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdaddr20only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
|
|
|
|
mnemonic#"$M3\t$R1, $BD2", []> {
|
2013-07-25 16:57:02 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
2013-08-01 18:39:40 +08:00
|
|
|
let CCMaskLast = 1;
|
2013-07-25 16:57:02 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondStoreRSY, but used for the raw assembly form. The condition-code
|
|
|
|
// mask is the third operand rather than being part of the mnemonic.
|
|
|
|
class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdaddr20only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$R1, $BD2, $M3", []> {
|
2013-07-25 16:57:02 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondStoreRSY, but with a fixed CC mask.
|
2016-11-09 02:30:50 +08:00
|
|
|
class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
2013-07-25 16:57:02 +08:00
|
|
|
AddressingMode mode = bdaddr20only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $BD2", []> {
|
2013-07-25 16:57:02 +08:00
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
2016-11-09 02:30:50 +08:00
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdaddr20only> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
|
|
|
|
def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
|
2013-07-25 16:57:02 +08:00
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
|
|
|
|
: InstI<opcode, (outs), (ins imm:$I1),
|
2016-12-03 02:19:22 +08:00
|
|
|
mnemonic#"\t$I1", []>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
2016-11-09 04:17:02 +08:00
|
|
|
class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
|
|
|
|
: InstRR<opcode, (outs), (ins cls:$R1),
|
|
|
|
mnemonic#"\t$R1", []> {
|
|
|
|
let R2 = 0;
|
|
|
|
}
|
|
|
|
|
2016-12-03 02:21:53 +08:00
|
|
|
class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
|
|
|
SDPatternOperator operator>
|
|
|
|
: InstRRE<opcode, (outs), (ins cls:$R1),
|
|
|
|
mnemonic#"\t$R1", [(operator cls:$R1)]> {
|
|
|
|
let R2 = 0;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class SideEffectUnaryS<string mnemonic, bits<16> opcode,
|
2016-12-03 02:21:53 +08:00
|
|
|
SDPatternOperator operator, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdaddr12only>
|
|
|
|
: InstS<opcode, (outs), (ins mode:$BD2),
|
|
|
|
mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class SideEffectAddressS<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
AddressingMode mode = bdaddr12only>
|
|
|
|
: InstS<opcode, (outs), (ins mode:$BD2),
|
|
|
|
mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
|
|
|
class LoadAddressRX<string mnemonic, bits<8> opcode,
|
|
|
|
SDPatternOperator operator, AddressingMode mode>
|
|
|
|
: InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set GR64:$R1, (operator mode:$XBD2))]>;
|
|
|
|
|
|
|
|
class LoadAddressRXY<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator, AddressingMode mode>
|
|
|
|
: InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set GR64:$R1, (operator mode:$XBD2))]>;
|
|
|
|
|
|
|
|
multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
|
|
|
|
bits<16> rxyOpcode, SDPatternOperator operator> {
|
|
|
|
let DispKey = mnemonic in {
|
|
|
|
let DispSize = "12" in
|
|
|
|
def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
|
|
|
|
let DispSize = "20" in
|
|
|
|
def Y : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
class LoadAddressRIL<string mnemonic, bits<12> opcode,
|
|
|
|
SDPatternOperator operator>
|
|
|
|
: InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
|
|
|
|
mnemonic#"\t$R1, $RI2",
|
|
|
|
[(set GR64:$R1, (operator pcrel32:$RI2))]>;
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
|
2016-11-09 02:36:31 +08:00
|
|
|
mnemonic#"\t$R1, $R2",
|
2013-07-03 18:10:02 +08:00
|
|
|
[(set cls1:$R1, (operator cls2:$R2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#cls1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "reg";
|
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
|
2016-11-09 02:36:31 +08:00
|
|
|
mnemonic#"\t$R1, $R2",
|
2013-07-03 18:10:02 +08:00
|
|
|
[(set cls1:$R1, (operator cls2:$R2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#cls1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "reg";
|
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
2017-05-10 20:41:12 +08:00
|
|
|
class UnaryMemRRFc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
|
|
|
|
mnemonic#"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let M3 = 0;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
|
|
|
|
mnemonic#"\t$R1, $I2",
|
|
|
|
[(set cls:$R1, (operator imm:$I2))]>;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
|
|
|
|
mnemonic#"\t$R1, $I2",
|
|
|
|
[(set cls:$R1, (operator imm:$I2))]>;
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
|
|
|
|
mnemonic#"\t$R1, $RI2",
|
|
|
|
[(set cls:$R1, (operator pcrel32:$RI2))]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
|
|
// complex.
|
|
|
|
let AddedComplexity = 7;
|
|
|
|
}
|
|
|
|
|
2013-07-25 17:04:52 +08:00
|
|
|
class CondUnaryRSY<string mnemonic, bits<16> opcode,
|
2013-07-31 20:38:08 +08:00
|
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
bits<5> bytes, AddressingMode mode = bdaddr20only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSYb<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
|
|
|
|
mnemonic#"$M3\t$R1, $BD2",
|
|
|
|
[(set cls:$R1,
|
|
|
|
(z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
|
|
|
|
cond4:$valid, cond4:$M3))]> {
|
2013-07-25 17:04:52 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
2013-08-01 18:39:40 +08:00
|
|
|
let CCMaskLast = 1;
|
2013-07-25 17:04:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondUnaryRSY, but used for the raw assembly form. The condition-code
|
|
|
|
// mask is the third operand rather than being part of the mnemonic.
|
|
|
|
class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdaddr20only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$R1, $BD2, $M3", []> {
|
2013-07-25 17:04:52 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondUnaryRSY, but with a fixed CC mask.
|
2016-11-09 02:30:50 +08:00
|
|
|
class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
2013-07-25 17:04:52 +08:00
|
|
|
AddressingMode mode = bdaddr20only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $BD2", []> {
|
2013-07-25 17:04:52 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
2016-11-09 02:30:50 +08:00
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
2013-07-25 17:04:52 +08:00
|
|
|
}
|
|
|
|
|
2016-11-09 02:30:50 +08:00
|
|
|
multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdaddr20only> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
|
|
|
|
def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdxaddr12only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set cls:$R1, (operator mode:$XBD2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, bits<5> bytes>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2015-05-06 03:23:40 +08:00
|
|
|
let M3 = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdxaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set cls:$R1, (operator mode:$XBD2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
2013-07-03 18:10:02 +08:00
|
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
bits<5> bytes> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
2013-07-03 18:10:02 +08:00
|
|
|
def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-07-03 18:10:02 +08:00
|
|
|
def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
|
|
|
|
bdxaddr20pair>;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr, Immediate imm, bits<4> type = 0>
|
|
|
|
: InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
|
|
|
|
mnemonic#"\t$V1, $I2",
|
|
|
|
[(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
|
|
|
|
let M3 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, Immediate imm>
|
|
|
|
: InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$V1, $I2, $M3", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
|
|
|
|
bits<4> m5 = 0>
|
|
|
|
: InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
|
|
|
|
mnemonic#"\t$V1, $V2",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
|
|
|
|
let M3 = type;
|
|
|
|
let M4 = m4;
|
|
|
|
let M5 = m5;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
|
|
|
|
bits<4> m5 = 0>
|
|
|
|
: InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$V1, $V2, $M3", []> {
|
|
|
|
let M4 = m4;
|
|
|
|
let M5 = m5;
|
|
|
|
}
|
|
|
|
|
|
|
|
class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
|
|
|
|
: InstVRRa<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $V2, $M3, $M4", []> {
|
|
|
|
let M5 = m5;
|
|
|
|
}
|
|
|
|
|
2016-10-19 20:57:46 +08:00
|
|
|
// Declare a pair of instructions, one which sets CC and one which doesn't.
|
|
|
|
// The CC-setting form ends with "S" and sets the low bit of M5.
|
|
|
|
// The form that does not set CC has an extra operand to optionally allow
|
|
|
|
// specifying arbitrary M5 values in assembler.
|
|
|
|
multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
SDPatternOperator operator_cc,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type> {
|
|
|
|
let M3 = type, M4 = 0 in
|
|
|
|
def "" : InstVRRa<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $M5", []>;
|
|
|
|
def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
|
|
|
|
(!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
|
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2",
|
|
|
|
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
let Defs = [CC] in
|
2016-10-19 20:57:46 +08:00
|
|
|
def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
|
|
|
|
type, 0, 1>;
|
2015-05-06 03:23:40 +08:00
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
|
|
|
|
let M4 = 0 in
|
|
|
|
def "" : InstVRRa<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $M3, $M5", []>;
|
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
|
|
|
|
(!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
|
|
|
|
imm32zx4:$M3, 0)>;
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr, bits<5> bytes, bits<4> type = 0>
|
|
|
|
: InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$V1, $XBD2",
|
|
|
|
[(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
|
|
|
|
let M3 = type;
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$V1, $XBD2, $M3", []> {
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
|
2016-12-03 02:19:22 +08:00
|
|
|
mnemonic##"\t$R1, $XBD2", []>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
|
|
|
class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
|
|
|
|
mnemonic##"\t$R1, $RI2", []> {
|
|
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
|
|
// complex.
|
|
|
|
let AddedComplexity = 7;
|
|
|
|
}
|
|
|
|
|
2016-11-28 22:01:51 +08:00
|
|
|
class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
|
|
|
|
Immediate imm1, Immediate imm2>
|
|
|
|
: InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
|
2016-12-03 02:19:22 +08:00
|
|
|
mnemonic#"\t$I1, $I2", []>;
|
2016-11-28 22:01:51 +08:00
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator, Immediate imm>
|
|
|
|
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
|
2016-12-03 02:19:22 +08:00
|
|
|
mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
2017-05-10 20:40:15 +08:00
|
|
|
class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
|
|
|
|
: InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
|
|
|
|
mnemonic##"\t$BDL1, $BD2", []>;
|
|
|
|
|
2017-05-10 20:42:45 +08:00
|
|
|
class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
|
|
|
|
: InstSSb<opcode,
|
|
|
|
(outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
|
|
|
|
mnemonic##"\t$BDL1, $BDL2", []>;
|
|
|
|
|
|
|
|
class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
|
|
|
|
: InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
|
|
|
|
mnemonic##"\t$BD1, $BDL2", []>;
|
|
|
|
|
2017-05-10 20:40:15 +08:00
|
|
|
class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
|
|
|
|
mnemonic#"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src, $R2 = $R2src";
|
|
|
|
let DisableEncoding = "$R1src, $R2src";
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:42:00 +08:00
|
|
|
class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
|
|
|
|
mnemonic#"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R2 = $R2src";
|
|
|
|
let DisableEncoding = "$R2src";
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:40:15 +08:00
|
|
|
class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
|
|
|
|
mnemonic#"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src, $R2 = $R2src";
|
|
|
|
let DisableEncoding = "$R1src, $R2src";
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:41:12 +08:00
|
|
|
class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
|
|
|
|
mnemonic#"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src, $R2 = $R2src";
|
|
|
|
let DisableEncoding = "$R1src, $R2src";
|
|
|
|
let M3 = 0;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
2016-11-09 02:36:31 +08:00
|
|
|
mnemonic#"\t$R1, $R2",
|
2013-05-14 17:28:21 +08:00
|
|
|
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#cls1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "reg";
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
2016-11-09 02:36:31 +08:00
|
|
|
mnemonic#"\t$R1, $R2",
|
2013-05-14 17:28:21 +08:00
|
|
|
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#cls1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "reg";
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2016-11-09 02:36:31 +08:00
|
|
|
class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2,
|
|
|
|
RegisterOperand cls3>
|
|
|
|
: InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
|
|
|
|
mnemonic#"\t$R1, $R2, $R3",
|
|
|
|
[(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
|
|
|
|
let M4 = 0;
|
2013-08-21 16:58:08 +08:00
|
|
|
}
|
2013-07-20 00:21:55 +08:00
|
|
|
|
|
|
|
multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2> {
|
|
|
|
let NumOpsKey = mnemonic in {
|
|
|
|
let NumOpsValue = "3" in
|
2016-11-09 02:36:31 +08:00
|
|
|
def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
|
2013-07-20 00:21:55 +08:00
|
|
|
Requires<[FeatureDistinctOps]>;
|
|
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
|
|
def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-20 00:24:22 +08:00
|
|
|
multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2> {
|
|
|
|
let NumOpsKey = mnemonic in {
|
|
|
|
let NumOpsValue = "3" in
|
2016-11-09 02:36:31 +08:00
|
|
|
def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
|
2013-07-20 00:24:22 +08:00
|
|
|
Requires<[FeatureDistinctOps]>;
|
|
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
|
|
def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:36:31 +08:00
|
|
|
class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2,
|
|
|
|
RegisterOperand cls3>
|
|
|
|
: InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
|
|
|
|
mnemonic#"\t$R1, $R3, $R2",
|
|
|
|
[(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
|
|
|
|
let M4 = 0;
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:41:12 +08:00
|
|
|
class BinaryMemRRFc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2, Immediate imm>
|
|
|
|
: InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
|
|
|
|
mnemonic#"\t$R1, $R2, $M3", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2> {
|
|
|
|
def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
|
|
|
|
def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:36:31 +08:00
|
|
|
class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2>
|
|
|
|
: InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
|
|
|
|
mnemonic#"\t$R1, $M3, $R2", []> {
|
|
|
|
let M4 = 0;
|
|
|
|
}
|
|
|
|
|
2016-11-28 21:34:08 +08:00
|
|
|
class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2>
|
|
|
|
: InstRRFc<opcode, (outs cls1:$R1),
|
|
|
|
(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
|
|
|
|
mnemonic#"$M3\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let CCMaskLast = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondBinaryRRF, but used for the raw assembly form. The condition-code
|
|
|
|
// mask is the third operand rather than being part of the mnemonic.
|
|
|
|
class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2>
|
|
|
|
: InstRRFc<opcode, (outs cls1:$R1),
|
|
|
|
(ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$R1, $R2, $M3", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondBinaryRRF, but with a fixed CC mask.
|
|
|
|
class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let isAsmParserOnly = V.alternate;
|
|
|
|
let M3 = V.ccmask;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2> {
|
|
|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
|
|
|
|
def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
|
|
mnemonic#"\t$R1, $I2",
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2013-07-20 00:32:12 +08:00
|
|
|
class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
|
|
|
: InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
|
|
|
|
mnemonic#"\t$R1, $R3, $I2",
|
|
|
|
[(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
|
|
|
|
|
|
|
|
multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm> {
|
|
|
|
let NumOpsKey = mnemonic in {
|
|
|
|
let NumOpsValue = "3" in
|
|
|
|
def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
|
|
|
|
Requires<[FeatureDistinctOps]>;
|
|
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
|
|
def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-28 21:34:08 +08:00
|
|
|
class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
|
|
|
: InstRIEg<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
|
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|
|
mnemonic#"$M3\t$R1, $I2",
|
|
|
|
[(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
|
|
|
|
cond4:$valid, cond4:$M3))]> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let CCMaskLast = 1;
|
|
|
|
}
|
|
|
|
|
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|
|
// Like CondBinaryRIE, but used for the raw assembly form. The condition-code
|
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|
|
// mask is the third operand rather than being part of the mnemonic.
|
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|
|
class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
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|
|
Immediate imm>
|
|
|
|
: InstRIEg<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, imm:$I2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$R1, $I2, $M3", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
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|
|
// Like CondBinaryRIE, but with a fixed CC mask.
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|
|
class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
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|
|
RegisterOperand cls, Immediate imm>
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|
|
: InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
|
|
mnemonic#V.suffix#"\t$R1, $I2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
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|
|
|
let DisableEncoding = "$R1src";
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|
|
let isAsmParserOnly = V.alternate;
|
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|
|
let M3 = V.ccmask;
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|
|
|
}
|
|
|
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|
|
|
multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
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|
|
RegisterOperand cls, Immediate imm> {
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|
|
let isCodeGenOnly = 1 in
|
|
|
|
def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
|
|
|
|
def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
|
|
mnemonic#"\t$R1, $I2",
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2014-07-10 19:29:23 +08:00
|
|
|
class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
|
|
|
|
mnemonic#"\t$R1, $BD2",
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
|
2014-07-10 19:29:23 +08:00
|
|
|
let R3 = 0;
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
|
|
[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
|
2014-07-10 19:29:23 +08:00
|
|
|
|
|
|
|
multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls> {
|
|
|
|
let NumOpsKey = mnemonic in {
|
|
|
|
let NumOpsValue = "3" in
|
|
|
|
def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
|
|
|
|
Requires<[FeatureDistinctOps]>;
|
|
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
|
|
def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
2013-05-07 00:15:19 +08:00
|
|
|
AddressingMode mode = bdxaddr12only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set cls:$R1, (operator cls:$R1src,
|
|
|
|
(load bdxaddr12only:$XBD2)))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2015-05-06 03:23:40 +08:00
|
|
|
let M3 = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
2013-05-07 00:15:19 +08:00
|
|
|
AddressingMode mode = bdxaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls,
|
2013-07-03 18:10:02 +08:00
|
|
|
SDPatternOperator load, bits<5> bytes> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
2013-07-03 18:10:02 +08:00
|
|
|
def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
|
|
|
|
bdxaddr12pair>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-07-03 18:10:02 +08:00
|
|
|
def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
|
2013-05-07 00:15:19 +08:00
|
|
|
bdxaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
|
|
Operand imm, AddressingMode mode = bdaddr12only>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
|
|
mnemonic#"\t$BD1, $I2",
|
|
|
|
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
Operand imm, AddressingMode mode = bdaddr20only>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
|
|
mnemonic#"\t$BD1, $I2",
|
|
|
|
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
|
|
|
|
bits<16> siyOpcode, SDPatternOperator operator,
|
|
|
|
Operand imm> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-12-03 02:24:16 +08:00
|
|
|
class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
|
|
|
|
: InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
|
|
|
|
mnemonic#"\t$R3, $BD1, $BD2", []> {
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr, bits<4> type>
|
|
|
|
: InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
|
|
|
|
mnemonic#"\t$V1, $I2, $I3",
|
|
|
|
[(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
|
|
|
|
let M4 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRIb<opcode, (outs VR128:$V1),
|
|
|
|
(ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $I2, $I3, $M4", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type>
|
|
|
|
: InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
|
|
|
|
mnemonic#"\t$V1, $V3, $I2",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
|
|
|
|
imm32zx16:$I2)))]> {
|
|
|
|
let M4 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRIc<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $V3, $I2, $M4", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
|
|
|
|
: InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
|
|
|
|
mnemonic#"\t$V1, $V2, $I3",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
imm32zx12:$I3)))]> {
|
|
|
|
let M4 = type;
|
|
|
|
let M5 = m5;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRIe<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
|
|
|
|
|
|
|
|
class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
|
|
|
|
: InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $M5",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
imm32zx12:$M5)))]> {
|
|
|
|
let M3 = type;
|
|
|
|
let M4 = m4;
|
2015-05-06 03:23:40 +08:00
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRa<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type = 0,
|
|
|
|
bits<4> modifier = 0>
|
|
|
|
: InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3))))]> {
|
|
|
|
let M4 = type;
|
|
|
|
let M5 = modifier;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Declare a pair of instructions, one which sets CC and one which doesn't.
|
|
|
|
// The CC-setting form ends with "S" and sets the low bit of M5.
|
|
|
|
multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
SDPatternOperator operator_cc, TypedReg tr1,
|
2016-10-19 20:57:46 +08:00
|
|
|
TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
|
|
|
|
def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
|
|
|
|
!and (modifier, 14)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
let Defs = [CC] in
|
|
|
|
def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
|
2016-10-19 20:57:46 +08:00
|
|
|
!add (!and (modifier, 14), 1)>;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRb<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
|
|
|
|
|
2016-10-19 20:57:46 +08:00
|
|
|
// Declare a pair of instructions, one which sets CC and one which doesn't.
|
|
|
|
// The CC-setting form ends with "S" and sets the low bit of M5.
|
|
|
|
// The form that does not set CC has an extra operand to optionally allow
|
|
|
|
// specifying arbitrary M5 values in assembler.
|
|
|
|
multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
SDPatternOperator operator_cc,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type> {
|
|
|
|
let M4 = type in
|
|
|
|
def "" : InstVRRb<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M5", []>;
|
|
|
|
def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
|
|
|
|
(!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
|
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
|
|
|
|
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
|
|
|
|
tr2.op:$V3, 0)>;
|
|
|
|
let Defs = [CC] in
|
|
|
|
def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
|
2015-05-06 03:23:40 +08:00
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
|
|
|
|
def "" : InstVRRb<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
|
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
|
|
|
|
(!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
|
|
|
|
imm32zx4:$M4, 0)>;
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
|
|
|
|
bits<4> m6 = 0>
|
|
|
|
: InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3))))]> {
|
|
|
|
let M4 = type;
|
|
|
|
let M5 = m5;
|
|
|
|
let M6 = m6;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
|
|
|
|
bits<4> m6 = 0>
|
|
|
|
: InstVRRc<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M4", []> {
|
|
|
|
let M5 = m5;
|
|
|
|
let M6 = m6;
|
|
|
|
}
|
|
|
|
|
|
|
|
class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
|
|
|
|
: InstVRRc<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
|
|
|
|
let M6 = m6;
|
|
|
|
}
|
|
|
|
|
2016-10-19 20:57:46 +08:00
|
|
|
// Declare a pair of instructions, one which sets CC and one which doesn't.
|
|
|
|
// The CC-setting form ends with "S" and sets the low bit of M5.
|
2015-05-06 03:23:40 +08:00
|
|
|
multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
SDPatternOperator operator_cc, TypedReg tr1,
|
|
|
|
TypedReg tr2, bits<4> type, bits<4> m5,
|
2016-10-19 20:57:46 +08:00
|
|
|
bits<4> modifier = 0> {
|
|
|
|
def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
|
|
|
|
m5, !and (modifier, 14)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
let Defs = [CC] in
|
|
|
|
def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
|
2016-10-19 20:57:46 +08:00
|
|
|
m5, !add (!and (modifier, 14), 1)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRc<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
|
|
|
|
imm32zx4:$M6),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr>
|
|
|
|
: InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
|
|
|
|
mnemonic#"\t$V1, $R2, $R3",
|
|
|
|
[(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
|
|
|
|
|
|
|
|
class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type>
|
|
|
|
: InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
|
|
|
|
mnemonic#"\t$V1, $V3, $BD2",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
|
|
|
|
shift12only:$BD2)))]> {
|
|
|
|
let M4 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRSa<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
bits<5> bytes>
|
|
|
|
: InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
|
|
|
|
mnemonic#"\t$V1, $R3, $BD2",
|
|
|
|
[(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
|
|
|
|
let M4 = 0;
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr, bits<4> type>
|
|
|
|
: InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
|
|
|
|
mnemonic#"\t$R1, $V3, $BD2",
|
|
|
|
[(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
|
|
|
|
let M4 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRSc<opcode, (outs GR64:$R1),
|
|
|
|
(ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
|
|
|
|
mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr, bits<5> bytes>
|
|
|
|
: InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$V1, $XBD2, $M3",
|
|
|
|
[(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
|
|
|
|
imm32zx4:$M3)))]> {
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
|
|
|
|
Immediate index>
|
|
|
|
: InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
|
|
|
|
mnemonic#"\t$V1, $VBD2, $M3", []> {
|
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class StoreBinaryVRX<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator, TypedReg tr, bits<5> bytes,
|
|
|
|
Immediate index>
|
|
|
|
: InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
|
|
|
|
mnemonic#"\t$V1, $XBD2, $M3",
|
|
|
|
[(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
|
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class MemoryBinarySSd<string mnemonic, bits<8> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstSSd<opcode, (outs),
|
|
|
|
(ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
|
|
|
|
mnemonic#"\t$RBD1, $BD2, $R3", []>;
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
|
2016-11-09 02:36:31 +08:00
|
|
|
mnemonic#"\t$R1, $R2",
|
2013-07-03 18:10:02 +08:00
|
|
|
[(operator cls1:$R1, cls2:$R2)]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#cls1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "reg";
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
|
2016-11-09 02:36:31 +08:00
|
|
|
mnemonic#"\t$R1, $R2",
|
2013-07-03 18:10:02 +08:00
|
|
|
[(operator cls1:$R1, cls2:$R2)]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#cls1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "reg";
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
|
|
|
|
mnemonic#"\t$R1, $I2",
|
|
|
|
[(operator cls:$R1, imm:$I2)]> {
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
|
|
|
|
mnemonic#"\t$R1, $I2",
|
|
|
|
[(operator cls:$R1, imm:$I2)]> {
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
|
|
|
}
|
2013-05-07 00:15:19 +08:00
|
|
|
|
|
|
|
class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, SDPatternOperator load>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
|
|
|
|
mnemonic#"\t$R1, $RI2",
|
|
|
|
[(operator cls:$R1, (load pcrel32:$RI2))]> {
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
|
|
// complex.
|
|
|
|
let AddedComplexity = 7;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
2013-05-07 00:15:19 +08:00
|
|
|
AddressingMode mode = bdxaddr12only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(operator cls:$R1, (load mode:$XBD2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2015-05-06 03:23:40 +08:00
|
|
|
let M3 = 0;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
2013-05-07 00:15:19 +08:00
|
|
|
AddressingMode mode = bdxaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(operator cls:$R1, (load mode:$XBD2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls,
|
2013-07-03 18:10:02 +08:00
|
|
|
SDPatternOperator load, bits<5> bytes> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
|
2013-07-03 18:10:02 +08:00
|
|
|
load, bytes, bdxaddr12pair>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
|
2013-07-03 18:10:02 +08:00
|
|
|
load, bytes, bdxaddr20pair>;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:42:45 +08:00
|
|
|
class CompareSSb<string mnemonic, bits<8> opcode>
|
|
|
|
: InstSSb<opcode,
|
|
|
|
(outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
|
|
|
|
mnemonic##"\t$BDL1, $BDL2", []> {
|
|
|
|
let isCompare = 1;
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
|
|
SDPatternOperator load, Immediate imm,
|
|
|
|
AddressingMode mode = bdaddr12only>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
|
|
mnemonic#"\t$BD1, $I2",
|
|
|
|
[(operator (load mode:$BD1), imm:$I2)]> {
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
SDPatternOperator load, Immediate imm>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
|
|
|
|
mnemonic#"\t$BD1, $I2",
|
|
|
|
[(operator (load bdaddr12only:$BD1), imm:$I2)]> {
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
SDPatternOperator load, Immediate imm,
|
|
|
|
AddressingMode mode = bdaddr20only>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
|
|
mnemonic#"\t$BD1, $I2",
|
|
|
|
[(operator (load mode:$BD1), imm:$I2)]> {
|
2013-07-25 17:34:38 +08:00
|
|
|
let isCompare = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
|
|
|
|
SDPatternOperator operator, SDPatternOperator load,
|
|
|
|
Immediate imm> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic in {
|
|
|
|
let DispSize = "12" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
|
|
|
|
bdaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr, bits<4> type>
|
|
|
|
: InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
|
|
|
|
mnemonic#"\t$V1, $V2",
|
|
|
|
[(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
|
|
|
|
let isCompare = 1;
|
|
|
|
let M3 = type;
|
|
|
|
let M4 = 0;
|
|
|
|
let M5 = 0;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
|
|
|
|
mnemonic#"\t$V1, $V2, $M3", []> {
|
|
|
|
let isCompare = 1;
|
|
|
|
let M4 = 0;
|
|
|
|
let M5 = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRa<opcode, (outs),
|
|
|
|
(ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $V2, $M3, $M4", []> {
|
|
|
|
let isCompare = 1;
|
|
|
|
let M5 = 0;
|
|
|
|
}
|
|
|
|
|
2016-06-29 15:29:07 +08:00
|
|
|
class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $XBD2",
|
|
|
|
[(operator cls:$R1, bdxaddr12only:$XBD2)]> {
|
|
|
|
let M3 = 0;
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:42:45 +08:00
|
|
|
class TestRSL<string mnemonic, bits<16> opcode>
|
|
|
|
: InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
|
|
|
|
mnemonic#"\t$BDL1", []> {
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
|
|
|
|
: InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
|
|
|
|
shift12only:$BD2, imm32zx4:$I3),
|
|
|
|
mnemonic##"\t$BDL1, $BD2, $I3", []>;
|
|
|
|
|
2017-05-10 20:42:00 +08:00
|
|
|
class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2,
|
|
|
|
RegisterOperand cls3>
|
|
|
|
: InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
|
|
|
|
(ins cls1:$R1src, cls2:$R2src, cls3:$R3src),
|
|
|
|
mnemonic#"\t$R1, $R3, $R2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
|
|
|
|
let DisableEncoding = "$R1src, $R2src, $R3src";
|
|
|
|
let M4 = 0;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2,
|
|
|
|
Immediate imm>
|
|
|
|
: InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
|
2016-12-03 02:19:22 +08:00
|
|
|
mnemonic#"\t$R1, $R2, $M3", []>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
2017-05-10 20:41:12 +08:00
|
|
|
class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2,
|
|
|
|
Immediate imm>
|
|
|
|
: InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
|
|
|
|
(ins cls1:$R1src, cls2:$R2src, imm:$M3),
|
|
|
|
mnemonic#"\t$R1, $R2, $M3", []> {
|
|
|
|
let Constraints = "$R1 = $R1src, $R2 = $R2src";
|
|
|
|
let DisableEncoding = "$R1src, $R2src";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2> {
|
|
|
|
def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
|
|
|
|
def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstSSF<opcode, (outs),
|
|
|
|
(ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
|
2016-12-03 02:19:22 +08:00
|
|
|
mnemonic#"\t$BD1, $BD2, $R3", []>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
2016-11-09 02:36:31 +08:00
|
|
|
class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2>
|
|
|
|
: InstRRFe<opcode, (outs cls1:$R1),
|
|
|
|
(ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$R1, $M3, $R2, $M4", []>;
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class TernaryRRD<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
|
2016-11-09 02:36:31 +08:00
|
|
|
mnemonic#"\t$R1, $R3, $R2",
|
2013-05-14 17:28:21 +08:00
|
|
|
[(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "reg";
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
|
|
|
|
bits<5> bytes, AddressingMode mode = bdaddr12only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSb<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $M3, $BD2", []> {
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
|
|
|
bits<5> bytes, AddressingMode mode = bdaddr20only>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRSYb<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $M3, $BD2", []> {
|
[SystemZ] Add support for missing instructions
Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.
Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.
Reviewers: uweigand
Subscribers: koriakin, llvm-commits
Differential Revision: http://reviews.llvm.org/D22050
llvm-svn: 274869
2016-07-09 00:18:40 +08:00
|
|
|
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
|
|
|
RegisterOperand cls, bits<5> bytes> {
|
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
|
|
|
def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
|
|
|
|
let DispSize = "20" in
|
|
|
|
def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-10 20:40:15 +08:00
|
|
|
class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
|
|
|
|
(ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src, $R3 = $R3src";
|
|
|
|
let DisableEncoding = "$R1src, $R3src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
|
|
|
|
(ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
|
|
|
let Constraints = "$R1 = $R1src, $R3 = $R3src";
|
|
|
|
let DisableEncoding = "$R1src, $R3src";
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
2013-07-03 18:10:02 +08:00
|
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRXF<opcode, (outs cls:$R1),
|
|
|
|
(ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $XBD2",
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, cls:$R3,
|
|
|
|
(load bdxaddr12only:$XBD2)))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = mnemonic#"r"#cls;
|
2013-07-03 18:10:02 +08:00
|
|
|
let OpType = "mem";
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
2013-07-03 18:10:02 +08:00
|
|
|
let AccessBytes = bytes;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
|
|
|
|
: InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
|
|
|
|
mnemonic#"\t$V1, $I2, $M3",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
|
|
|
|
imm:$I2, index:$M3)))]> {
|
|
|
|
let Constraints = "$V1 = $V1src";
|
|
|
|
let DisableEncoding = "$V1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type>
|
|
|
|
: InstVRId<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $I4",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3),
|
|
|
|
imm32zx8:$I4)))]> {
|
|
|
|
let M5 = type;
|
|
|
|
}
|
|
|
|
|
|
|
|
class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
|
|
|
|
: InstVRRa<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $M4, $M5",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
imm32zx4:$M4,
|
|
|
|
imm32zx4:$M5)))],
|
|
|
|
m4or> {
|
|
|
|
let M3 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRa<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type,
|
|
|
|
SDPatternOperator m5mask, bits<4> m5or>
|
|
|
|
: InstVRRb<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M5",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3),
|
|
|
|
m5mask:$M5)))],
|
|
|
|
m5or> {
|
|
|
|
let M4 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 20:57:46 +08:00
|
|
|
// Declare a pair of instructions, one which sets CC and one which doesn't.
|
|
|
|
// The CC-setting form ends with "S" and sets the low bit of M5.
|
|
|
|
// Also create aliases to make use of M5 operand optional in assembler.
|
|
|
|
multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
SDPatternOperator operator_cc,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type,
|
|
|
|
bits<4> modifier = 0> {
|
2015-05-06 03:23:40 +08:00
|
|
|
def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
|
2016-10-19 20:57:46 +08:00
|
|
|
imm32zx4even, !and (modifier, 14)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
|
|
|
|
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
|
|
|
|
tr2.op:$V3, 0)>;
|
|
|
|
let Defs = [CC] in
|
|
|
|
def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
|
2016-10-19 20:57:46 +08:00
|
|
|
imm32zx4even, !add(!and (modifier, 14), 1)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
|
|
|
|
(!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
|
|
|
|
tr2.op:$V3, 0)>;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
|
|
|
|
def "" : InstVRRb<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
|
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
|
|
|
|
(!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
|
|
|
|
imm32zx4:$M4, 0)>;
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2>
|
|
|
|
: InstVRRc<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $M4",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3),
|
|
|
|
imm32zx4:$M4)))]> {
|
|
|
|
let M5 = 0;
|
|
|
|
let M6 = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type = 0>
|
|
|
|
: InstVRRd<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $V4",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3),
|
|
|
|
(tr1.vt tr1.op:$V4))))]> {
|
|
|
|
let M5 = type;
|
|
|
|
let M6 = 0;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRd<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
|
|
|
|
let M6 = 0;
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
|
|
|
|
: InstVRRe<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $V4",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3),
|
|
|
|
(tr1.vt tr1.op:$V4))))]> {
|
|
|
|
let M5 = m5;
|
|
|
|
let M6 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRRe<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
|
|
|
|
: InstVRSb<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
|
|
|
|
mnemonic#"\t$V1, $R3, $BD2",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
|
|
|
|
cls:$R3,
|
|
|
|
shift12only:$BD2)))]> {
|
|
|
|
let Constraints = "$V1 = $V1src";
|
|
|
|
let DisableEncoding = "$V1src";
|
|
|
|
let M4 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRSb<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
|
|
|
|
mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
|
|
|
|
let Constraints = "$V1 = $V1src";
|
|
|
|
let DisableEncoding = "$V1src";
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
|
|
|
|
Immediate index>
|
|
|
|
: InstVRV<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
|
|
|
|
mnemonic#"\t$V1, $VBD2, $M3", []> {
|
|
|
|
let Constraints = "$V1 = $V1src";
|
|
|
|
let DisableEncoding = "$V1src";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
|
|
|
|
: InstVRX<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
|
|
|
|
mnemonic#"\t$V1, $XBD2, $M3",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
|
|
|
|
bdxaddr12only:$XBD2,
|
|
|
|
index:$M3)))]> {
|
|
|
|
let Constraints = "$V1 = $V1src";
|
|
|
|
let DisableEncoding = "$V1src";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type>
|
|
|
|
: InstVRId<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $I4",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
|
|
|
|
(tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3),
|
|
|
|
imm32zx8:$I4)))]> {
|
|
|
|
let Constraints = "$V1 = $V1src";
|
|
|
|
let DisableEncoding = "$V1src";
|
|
|
|
let M5 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
|
|
|
|
: InstVRId<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V1src, VR128:$V2, VR128:$V3,
|
|
|
|
imm32zx8:$I4, imm32zx4:$M5),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
|
|
|
|
let Constraints = "$V1 = $V1src";
|
|
|
|
let DisableEncoding = "$V1src";
|
|
|
|
}
|
|
|
|
|
2015-05-06 03:23:40 +08:00
|
|
|
class QuaternaryVRRd<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
|
|
|
|
bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
|
|
|
|
: InstVRRd<opcode, (outs tr1.op:$V1),
|
|
|
|
(ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
|
|
|
|
(tr2.vt tr2.op:$V3),
|
|
|
|
(tr2.vt tr2.op:$V4),
|
|
|
|
m6mask:$M6)))],
|
|
|
|
m6or> {
|
|
|
|
let M5 = type;
|
|
|
|
}
|
|
|
|
|
2016-10-19 20:57:46 +08:00
|
|
|
// Declare a pair of instructions, one which sets CC and one which doesn't.
|
|
|
|
// The CC-setting form ends with "S" and sets the low bit of M6.
|
|
|
|
// Also create aliases to make use of M6 operand optional in assembler.
|
|
|
|
multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator,
|
|
|
|
SDPatternOperator operator_cc,
|
|
|
|
TypedReg tr1, TypedReg tr2, bits<4> type,
|
|
|
|
bits<4> modifier = 0> {
|
2015-05-06 03:23:40 +08:00
|
|
|
def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
|
2016-10-19 20:57:46 +08:00
|
|
|
imm32zx4even, !and (modifier, 14)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
|
|
|
|
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
|
|
|
|
tr2.op:$V3, tr2.op:$V4, 0)>;
|
|
|
|
let Defs = [CC] in
|
|
|
|
def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
|
2016-10-19 20:57:46 +08:00
|
|
|
imm32zx4even, !add (!and (modifier, 14), 1)>;
|
2015-05-06 03:23:40 +08:00
|
|
|
def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
|
|
|
|
(!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
|
|
|
|
tr2.op:$V3, tr2.op:$V4, 0)>;
|
|
|
|
}
|
|
|
|
|
2016-10-19 21:03:18 +08:00
|
|
|
multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
|
|
|
|
def "" : InstVRRd<opcode, (outs VR128:$V1),
|
|
|
|
(ins VR128:$V2, VR128:$V3, VR128:$V4,
|
|
|
|
imm32zx4:$M5, imm32zx4:$M6),
|
|
|
|
mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
|
|
|
|
def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
|
|
|
|
(!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
|
|
|
|
VR128:$V4, imm32zx4:$M5, 0)>;
|
|
|
|
}
|
|
|
|
|
2016-12-03 02:24:16 +08:00
|
|
|
class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
|
|
|
|
RegisterOperand cls>
|
|
|
|
: InstSSe<opcode, (outs),
|
|
|
|
(ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
|
|
|
|
mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
|
|
|
|
|
2013-12-24 23:14:05 +08:00
|
|
|
class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, AddressingMode mode = bdaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
|
|
[(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
|
2013-12-24 23:14:05 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, AddressingMode mode = bdaddr12only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
|
|
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, AddressingMode mode = bdaddr20only>
|
2016-11-09 02:32:50 +08:00
|
|
|
: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
|
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
|
|
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
2013-05-14 17:28:21 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
let mayLoad = 1;
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
|
|
|
SDPatternOperator operator, RegisterOperand cls> {
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispKey = mnemonic ## #cls in {
|
|
|
|
let DispSize = "12" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
|
2013-07-03 17:19:58 +08:00
|
|
|
let DispSize = "20" in
|
2013-05-07 00:15:19 +08:00
|
|
|
def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
|
|
RegisterOperand cls2>
|
2013-05-14 17:28:21 +08:00
|
|
|
: InstRIEf<opcode, (outs cls1:$R1),
|
2014-07-10 18:52:51 +08:00
|
|
|
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
|
|
|
|
imm32zx6:$I5),
|
2013-05-14 17:28:21 +08:00
|
|
|
mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2013-08-23 19:36:42 +08:00
|
|
|
class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
|
|
|
|
mnemonic##"\t$M1, $XBD2",
|
|
|
|
[(operator imm32zx4:$M1, bdxaddr20only:$XBD2)]>;
|
2013-08-23 19:36:42 +08:00
|
|
|
|
|
|
|
class PrefetchRILPC<string mnemonic, bits<12> opcode,
|
|
|
|
SDPatternOperator operator>
|
2016-11-09 02:30:50 +08:00
|
|
|
: InstRILc<opcode, (outs), (ins imm32zx4:$M1, pcrel32:$RI2),
|
|
|
|
mnemonic##"\t$M1, $RI2",
|
|
|
|
[(operator imm32zx4:$M1, pcrel32:$RI2)]> {
|
2013-08-23 19:36:42 +08:00
|
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
|
|
// complex.
|
|
|
|
let AddedComplexity = 7;
|
|
|
|
}
|
|
|
|
|
2016-11-28 22:01:51 +08:00
|
|
|
class BranchPreloadSMI<string mnemonic, bits<8> opcode>
|
|
|
|
: InstSMI<opcode, (outs),
|
|
|
|
(ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
|
|
|
|
mnemonic#"\t$M1, $RI2, $BD3", []>;
|
|
|
|
|
|
|
|
class BranchPreloadMII<string mnemonic, bits<8> opcode>
|
|
|
|
: InstMII<opcode, (outs),
|
|
|
|
(ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
|
|
|
|
mnemonic#"\t$M1, $RI2, $RI3", []>;
|
|
|
|
|
2013-08-07 19:03:34 +08:00
|
|
|
// A floating-point load-and test operation. Create both a normal unary
|
|
|
|
// operation and one that acts as a comparison against zero.
|
2015-05-06 03:28:34 +08:00
|
|
|
// Note that the comparison against zero operation is not available if we
|
|
|
|
// have vector support, since load-and-test instructions will partially
|
|
|
|
// clobber the target (vector) register.
|
2013-08-07 19:03:34 +08:00
|
|
|
multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
|
|
|
|
RegisterOperand cls> {
|
|
|
|
def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
|
2015-05-06 03:28:34 +08:00
|
|
|
let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
|
2013-08-07 19:03:34 +08:00
|
|
|
def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Pseudo instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// Convenience instructions that get lowered to real instructions
|
|
|
|
// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
|
|
|
|
// or SystemZInstrInfo::expandPostRAPseudo().
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class Pseudo<dag outs, dag ins, list<dag> pattern>
|
|
|
|
: InstSystemZ<0, outs, ins, "", pattern> {
|
|
|
|
let isPseudo = 1;
|
|
|
|
let isCodeGenOnly = 1;
|
|
|
|
}
|
|
|
|
|
2016-11-09 02:37:48 +08:00
|
|
|
// Like SideEffectBinarySIL, but expanded later.
|
|
|
|
class SideEffectBinarySILPseudo<SDPatternOperator operator, Immediate imm>
|
|
|
|
: Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
|
2016-12-03 02:19:22 +08:00
|
|
|
[(operator bdaddr12only:$BD1, imm:$I2)]>;
|
2016-11-09 02:37:48 +08:00
|
|
|
|
2013-10-01 21:02:28 +08:00
|
|
|
// Like UnaryRI, but expanded after RA depending on the choice of register.
|
|
|
|
class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
|
|
|
: Pseudo<(outs cls:$R1), (ins imm:$I2),
|
|
|
|
[(set cls:$R1, (operator imm:$I2))]>;
|
|
|
|
|
2013-10-01 23:00:44 +08:00
|
|
|
// Like UnaryRXY, but expanded after RA depending on the choice of register.
|
2013-10-01 19:26:28 +08:00
|
|
|
class UnaryRXYPseudo<string key, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdxaddr20only>
|
|
|
|
: Pseudo<(outs cls:$R1), (ins mode:$XBD2),
|
|
|
|
[(set cls:$R1, (operator mode:$XBD2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = key#"r"#cls;
|
2013-10-01 19:26:28 +08:00
|
|
|
let OpType = "mem";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
let HasIndex = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like UnaryRR, but expanded after RA depending on the choice of registers.
|
|
|
|
class UnaryRRPseudo<string key, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: Pseudo<(outs cls1:$R1), (ins cls2:$R2),
|
|
|
|
[(set cls1:$R1, (operator cls2:$R2))]> {
|
2016-11-09 02:36:31 +08:00
|
|
|
let OpKey = key#cls1;
|
2013-10-01 19:26:28 +08:00
|
|
|
let OpType = "reg";
|
|
|
|
}
|
|
|
|
|
2013-10-01 21:18:56 +08:00
|
|
|
// Like BinaryRI, but expanded after RA depending on the choice of register.
|
|
|
|
class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
|
|
|
: Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
}
|
|
|
|
|
2013-10-01 22:53:46 +08:00
|
|
|
// Like BinaryRIE, but expanded after RA depending on the choice of register.
|
|
|
|
class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
|
|
|
: Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
|
|
|
|
[(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
|
|
|
|
|
|
|
|
// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
|
|
|
|
multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
|
|
|
|
RegisterOperand cls, Immediate imm> {
|
|
|
|
let NumOpsKey = key in {
|
|
|
|
let NumOpsValue = "3" in
|
|
|
|
def K : BinaryRIEPseudo<null_frag, cls, imm>,
|
|
|
|
Requires<[FeatureHighWord, FeatureDistinctOps]>;
|
|
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
|
|
def "" : BinaryRIPseudo<operator, cls, imm>,
|
|
|
|
Requires<[FeatureHighWord]>;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-01 22:41:52 +08:00
|
|
|
// Like CompareRI, but expanded after RA depending on the choice of register.
|
|
|
|
class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
2016-11-28 21:40:08 +08:00
|
|
|
: Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
|
|
|
|
let isCompare = 1;
|
|
|
|
}
|
2013-10-01 22:41:52 +08:00
|
|
|
|
2013-10-01 23:00:44 +08:00
|
|
|
// Like CompareRXY, but expanded after RA depending on the choice of register.
|
|
|
|
class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
SDPatternOperator load, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdxaddr20only>
|
|
|
|
: Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
|
|
|
|
[(operator cls:$R1, (load mode:$XBD2))]> {
|
|
|
|
let mayLoad = 1;
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
let HasIndex = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
2016-11-28 21:34:08 +08:00
|
|
|
// Like CondBinaryRRF, but expanded after RA depending on the choice of
|
|
|
|
// register.
|
|
|
|
class CondBinaryRRFPseudo<RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: Pseudo<(outs cls1:$R1),
|
|
|
|
(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), []> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let CCMaskLast = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondBinaryRIE, but expanded after RA depending on the choice of
|
|
|
|
// register.
|
|
|
|
class CondBinaryRIEPseudo<RegisterOperand cls, Immediate imm>
|
|
|
|
: Pseudo<(outs cls:$R1),
|
|
|
|
(ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
|
|
|
|
[(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
|
|
|
|
cond4:$valid, cond4:$M3))]> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let CCMaskLast = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondUnaryRSY, but expanded after RA depending on the choice of
|
|
|
|
// register.
|
|
|
|
class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
bits<5> bytes, AddressingMode mode = bdaddr20only>
|
|
|
|
: Pseudo<(outs cls:$R1),
|
|
|
|
(ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
|
|
|
|
[(set cls:$R1,
|
|
|
|
(z_select_ccmask (operator mode:$BD2), cls:$R1src,
|
|
|
|
cond4:$valid, cond4:$R3))]> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
let mayLoad = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
let CCMaskLast = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like CondStoreRSY, but expanded after RA depending on the choice of
|
|
|
|
// register.
|
|
|
|
class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
|
|
|
|
AddressingMode mode = bdaddr20only>
|
|
|
|
: Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
|
|
|
|
let mayStore = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
let CCMaskLast = 1;
|
|
|
|
}
|
|
|
|
|
2013-10-01 23:00:44 +08:00
|
|
|
// Like StoreRXY, but expanded after RA depending on the choice of register.
|
2013-10-01 19:26:28 +08:00
|
|
|
class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
bits<5> bytes, AddressingMode mode = bdxaddr20only>
|
|
|
|
: Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
|
|
|
|
[(operator cls:$R1, mode:$XBD2)]> {
|
|
|
|
let mayStore = 1;
|
|
|
|
let Has20BitOffset = 1;
|
|
|
|
let HasIndex = 1;
|
|
|
|
let AccessBytes = bytes;
|
|
|
|
}
|
|
|
|
|
2013-10-01 22:20:41 +08:00
|
|
|
// Like RotateSelectRIEf, but expanded after RA depending on the choice
|
|
|
|
// of registers.
|
|
|
|
class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: Pseudo<(outs cls1:$R1),
|
2014-07-10 18:52:51 +08:00
|
|
|
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
|
|
|
|
imm32zx6:$I5),
|
2013-10-01 22:20:41 +08:00
|
|
|
[]> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
let DisableEncoding = "$R1src";
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
|
|
|
|
// the value of the PSW's 2-bit condition code field.
|
|
|
|
class SelectWrapper<RegisterOperand cls>
|
[SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken. We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities. For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2. If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3. Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.
Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll. Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.
The patch also makes it easier to reuse CC results from other instructions.
llvm-svn: 187495
2013-07-31 20:30:20 +08:00
|
|
|
: Pseudo<(outs cls:$dst),
|
2014-07-10 18:52:51 +08:00
|
|
|
(ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
|
[SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken. We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities. For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2. If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3. Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.
Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll. Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.
The patch also makes it easier to reuse CC results from other instructions.
llvm-svn: 187495
2013-07-31 20:30:20 +08:00
|
|
|
[(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
|
2014-07-10 18:52:51 +08:00
|
|
|
imm32zx4:$valid, imm32zx4:$cc))]> {
|
2013-05-07 00:15:19 +08:00
|
|
|
let usesCustomInserter = 1;
|
|
|
|
// Although the instructions used by these nodes do not in themselves
|
2013-05-22 21:38:45 +08:00
|
|
|
// change CC, the insertion requires new blocks, and CC cannot be live
|
|
|
|
// across them.
|
|
|
|
let Defs = [CC];
|
|
|
|
let Uses = [CC];
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
2013-06-27 17:27:40 +08:00
|
|
|
// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
|
|
|
|
multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
|
|
|
|
SDPatternOperator load, AddressingMode mode> {
|
|
|
|
let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
|
[SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken. We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities. For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2. If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3. Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.
Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll. Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.
The patch also makes it easier to reuse CC results from other instructions.
llvm-svn: 187495
2013-07-31 20:30:20 +08:00
|
|
|
def "" : Pseudo<(outs),
|
2014-07-10 18:52:51 +08:00
|
|
|
(ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
|
2013-06-27 17:27:40 +08:00
|
|
|
[(store (z_select_ccmask cls:$new, (load mode:$addr),
|
2014-07-10 18:52:51 +08:00
|
|
|
imm32zx4:$valid, imm32zx4:$cc),
|
[SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken. We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities. For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2. If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3. Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.
Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll. Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.
The patch also makes it easier to reuse CC results from other instructions.
llvm-svn: 187495
2013-07-31 20:30:20 +08:00
|
|
|
mode:$addr)]>;
|
|
|
|
def Inv : Pseudo<(outs),
|
2014-07-10 18:52:51 +08:00
|
|
|
(ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
|
2013-06-27 17:27:40 +08:00
|
|
|
[(store (z_select_ccmask (load mode:$addr), cls:$new,
|
2014-07-10 18:52:51 +08:00
|
|
|
imm32zx4:$valid, imm32zx4:$cc),
|
[SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken. We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities. For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2. If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3. Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.
Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll. Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.
The patch also makes it easier to reuse CC results from other instructions.
llvm-svn: 187495
2013-07-31 20:30:20 +08:00
|
|
|
mode:$addr)]>;
|
2013-06-27 17:27:40 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-05-07 00:15:19 +08:00
|
|
|
// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
|
|
|
|
// describe the second (non-memory) operand.
|
|
|
|
class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
dag pat, DAGOperand operand>
|
|
|
|
: Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
|
|
|
|
[(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
|
2013-05-22 21:38:45 +08:00
|
|
|
let Defs = [CC];
|
2013-05-07 00:15:19 +08:00
|
|
|
let Has20BitOffset = 1;
|
|
|
|
let mayLoad = 1;
|
|
|
|
let mayStore = 1;
|
|
|
|
let usesCustomInserter = 1;
|
2016-10-20 16:27:16 +08:00
|
|
|
let hasNoSchedulingInfo = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Specializations of AtomicLoadWBinary.
|
|
|
|
class AtomicLoadBinaryReg32<SDPatternOperator operator>
|
|
|
|
: AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
|
|
|
|
class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
|
|
|
|
: AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
|
|
|
|
class AtomicLoadBinaryReg64<SDPatternOperator operator>
|
|
|
|
: AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
|
|
|
|
class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
|
|
|
|
: AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
|
|
|
|
|
|
|
|
// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
|
|
|
|
// describe the second (non-memory) operand.
|
|
|
|
class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
|
|
|
|
DAGOperand operand>
|
|
|
|
: Pseudo<(outs GR32:$dst),
|
|
|
|
(ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
|
|
|
|
ADDR32:$negbitshift, uimm32:$bitsize),
|
|
|
|
[(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
|
|
|
|
ADDR32:$negbitshift, uimm32:$bitsize))]> {
|
2013-05-22 21:38:45 +08:00
|
|
|
let Defs = [CC];
|
2013-05-07 00:15:19 +08:00
|
|
|
let Has20BitOffset = 1;
|
|
|
|
let mayLoad = 1;
|
|
|
|
let mayStore = 1;
|
|
|
|
let usesCustomInserter = 1;
|
2016-10-20 16:27:16 +08:00
|
|
|
let hasNoSchedulingInfo = 1;
|
2013-05-07 00:15:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Specializations of AtomicLoadWBinary.
|
|
|
|
class AtomicLoadWBinaryReg<SDPatternOperator operator>
|
|
|
|
: AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
|
|
|
|
class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
|
|
|
|
: AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
|
2013-08-12 18:17:33 +08:00
|
|
|
|
2013-08-27 17:54:29 +08:00
|
|
|
// Define an instruction that operates on two fixed-length blocks of memory,
|
|
|
|
// and associated pseudo instructions for operating on blocks of any size.
|
|
|
|
// The Sequence form uses a straight-line sequence of instructions and
|
|
|
|
// the Loop form uses a loop of length-256 instructions followed by
|
|
|
|
// another instruction to handle the excess.
|
2013-08-12 18:17:33 +08:00
|
|
|
multiclass MemorySS<string mnemonic, bits<8> opcode,
|
2013-08-27 17:54:29 +08:00
|
|
|
SDPatternOperator sequence, SDPatternOperator loop> {
|
2017-05-10 20:40:15 +08:00
|
|
|
def "" : SideEffectBinarySSa<mnemonic, opcode>;
|
2016-10-20 16:27:16 +08:00
|
|
|
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
|
2013-08-27 17:54:29 +08:00
|
|
|
def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
|
|
|
|
imm64:$length),
|
|
|
|
[(sequence bdaddr12only:$dest, bdaddr12only:$src,
|
|
|
|
imm64:$length)]>;
|
|
|
|
def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
|
|
|
|
imm64:$length, GR64:$count256),
|
|
|
|
[(loop bdaddr12only:$dest, bdaddr12only:$src,
|
|
|
|
imm64:$length, GR64:$count256)]>;
|
|
|
|
}
|
2013-08-12 18:17:33 +08:00
|
|
|
}
|
2013-08-16 19:21:54 +08:00
|
|
|
|
|
|
|
// Define an instruction that operates on two strings, both terminated
|
|
|
|
// by the character in R0. The instruction processes a CPU-determinated
|
|
|
|
// number of bytes at a time and sets CC to 3 if the instruction needs
|
|
|
|
// to be repeated. Also define a pseudo instruction that represents
|
|
|
|
// the full loop (the main instruction plus the branch on CC==3).
|
|
|
|
multiclass StringRRE<string mnemonic, bits<16> opcode,
|
|
|
|
SDPatternOperator operator> {
|
2017-05-10 20:40:15 +08:00
|
|
|
let Uses = [R0L] in
|
|
|
|
def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;
|
2016-10-20 16:27:16 +08:00
|
|
|
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
|
2013-08-16 19:21:54 +08:00
|
|
|
def Loop : Pseudo<(outs GR64:$end),
|
|
|
|
(ins GR64:$start1, GR64:$start2, GR32:$char),
|
|
|
|
[(set GR64:$end, (operator GR64:$start1, GR64:$start2,
|
|
|
|
GR32:$char))]>;
|
|
|
|
}
|
2013-09-25 18:20:08 +08:00
|
|
|
|
|
|
|
// A pseudo instruction that is a direct alias of a real instruction.
|
|
|
|
// These aliases are used in cases where a particular register operand is
|
|
|
|
// fixed or where the same instruction is used with different register sizes.
|
|
|
|
// The size parameter is the size in bytes of the associated real instruction.
|
|
|
|
class Alias<int size, dag outs, dag ins, list<dag> pattern>
|
|
|
|
: InstSystemZ<size, outs, ins, "", pattern> {
|
|
|
|
let isPseudo = 1;
|
|
|
|
let isCodeGenOnly = 1;
|
|
|
|
}
|
2013-09-25 19:11:53 +08:00
|
|
|
|
2015-05-06 03:27:45 +08:00
|
|
|
class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
|
|
|
|
|
2015-05-06 03:28:34 +08:00
|
|
|
// An alias of a UnaryVRR*, but with different register sizes.
|
|
|
|
class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
|
|
|
|
: Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
|
|
|
|
[(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
|
|
|
|
|
|
|
|
// An alias of a UnaryVRX, but with different register sizes.
|
|
|
|
class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
|
|
|
|
AddressingMode mode = bdxaddr12only>
|
|
|
|
: Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
|
|
|
|
[(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
|
|
|
|
|
|
|
|
// An alias of a StoreVRX, but with different register sizes.
|
|
|
|
class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
|
|
|
|
AddressingMode mode = bdxaddr12only>
|
|
|
|
: Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
|
|
|
|
[(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
|
|
|
|
|
2013-09-25 19:11:53 +08:00
|
|
|
// An alias of a BinaryRI, but with different register sizes.
|
|
|
|
class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
|
|
|
: Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
}
|
|
|
|
|
|
|
|
// An alias of a BinaryRIL, but with different register sizes.
|
|
|
|
class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
|
|
|
: Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
}
|
2013-10-01 19:26:28 +08:00
|
|
|
|
[SystemZ] Add CodeGen support for integer vector types
This the first of a series of patches to add CodeGen support exploiting
the instructions of the z13 vector facility. This patch adds support
for the native integer vector types (v16i8, v8i16, v4i32, v2i64).
When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
(except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.
The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.
However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.
These alignment rules are not only implemented at the C language level
(implemented in clang), but also at the LLVM IR level. This is done
by selecting a different DataLayout string depending on whether the
vector ABI is in effect or not.
Based on a patch by Richard Sandiford.
llvm-svn: 236521
2015-05-06 03:25:42 +08:00
|
|
|
// An alias of a BinaryVRRf, but with different register sizes.
|
|
|
|
class BinaryAliasVRRf<RegisterOperand cls>
|
|
|
|
: Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
|
|
|
|
|
2013-11-23 01:28:28 +08:00
|
|
|
// An alias of a CompareRI, but with different register sizes.
|
|
|
|
class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
|
|
|
|
Immediate imm>
|
|
|
|
: Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
|
|
|
|
let isCompare = 1;
|
|
|
|
}
|
|
|
|
|
2013-10-01 19:26:28 +08:00
|
|
|
// An alias of a RotateSelectRIEf, but with different register sizes.
|
|
|
|
class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
|
|
|
|
: Alias<6, (outs cls1:$R1),
|
2014-07-10 18:52:51 +08:00
|
|
|
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
|
|
|
|
imm32zx6:$I5), []> {
|
2013-10-01 19:26:28 +08:00
|
|
|
let Constraints = "$R1 = $R1src";
|
|
|
|
}
|