2016-06-03 18:15:36 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
|
|
|
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE
|
|
|
|
|
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX
|
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
|
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
|
2011-05-04 05:11:17 +08:00
|
|
|
|
2017-12-11 23:35:40 +08:00
|
|
|
define i32 @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4 x i32> %F, <8 x i16> %G, <16 x i8> %H, i64 %I, i32* %loadptr) nounwind {
|
2016-06-03 18:15:36 +08:00
|
|
|
; X32-SSE-LABEL: f:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X32-SSE: # %bb.0:
|
2016-06-03 18:15:36 +08:00
|
|
|
; X32-SSE-NEXT: pushl %ebp
|
|
|
|
|
; X32-SSE-NEXT: movl %esp, %ebp
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-SSE-NEXT: pushl %esi
|
2016-06-03 18:15:36 +08:00
|
|
|
; X32-SSE-NEXT: andl $-16, %esp
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-SSE-NEXT: subl $16, %esp
|
|
|
|
|
; X32-SSE-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-SSE-NEXT: movl 12(%ebp), %eax
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-SSE-NEXT: movdqa 56(%ebp), %xmm4
|
|
|
|
|
; X32-SSE-NEXT: movdqa 40(%ebp), %xmm5
|
|
|
|
|
; X32-SSE-NEXT: movdqa 24(%ebp), %xmm6
|
|
|
|
|
; X32-SSE-NEXT: movl 8(%ebp), %edx
|
|
|
|
|
; X32-SSE-NEXT: movl 80(%ebp), %ecx
|
|
|
|
|
; X32-SSE-NEXT: movl (%ecx), %esi
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
; X32-SSE-NEXT: addps {{\.LCPI.*}}, %xmm0
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-SSE-NEXT: movntps %xmm0, (%edx)
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
; X32-SSE-NEXT: paddq {{\.LCPI.*}}, %xmm2
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-SSE-NEXT: addl (%ecx), %esi
|
|
|
|
|
; X32-SSE-NEXT: movntdq %xmm2, (%edx)
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
; X32-SSE-NEXT: addpd {{\.LCPI.*}}, %xmm1
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-SSE-NEXT: addl (%ecx), %esi
|
|
|
|
|
; X32-SSE-NEXT: movntpd %xmm1, (%edx)
|
|
|
|
|
; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm6
|
|
|
|
|
; X32-SSE-NEXT: addl (%ecx), %esi
|
|
|
|
|
; X32-SSE-NEXT: movntdq %xmm6, (%edx)
|
|
|
|
|
; X32-SSE-NEXT: paddw {{\.LCPI.*}}, %xmm5
|
|
|
|
|
; X32-SSE-NEXT: addl (%ecx), %esi
|
|
|
|
|
; X32-SSE-NEXT: movntdq %xmm5, (%edx)
|
|
|
|
|
; X32-SSE-NEXT: paddb {{\.LCPI.*}}, %xmm4
|
|
|
|
|
; X32-SSE-NEXT: addl (%ecx), %esi
|
|
|
|
|
; X32-SSE-NEXT: movntdq %xmm4, (%edx)
|
|
|
|
|
; X32-SSE-NEXT: addl (%ecx), %esi
|
|
|
|
|
; X32-SSE-NEXT: movntil %eax, (%edx)
|
|
|
|
|
; X32-SSE-NEXT: movl (%ecx), %eax
|
|
|
|
|
; X32-SSE-NEXT: addl %esi, %eax
|
|
|
|
|
; X32-SSE-NEXT: movsd %xmm3, (%edx)
|
|
|
|
|
; X32-SSE-NEXT: addl (%ecx), %eax
|
|
|
|
|
; X32-SSE-NEXT: leal -4(%ebp), %esp
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-SSE-NEXT: popl %esi
|
2016-06-03 18:15:36 +08:00
|
|
|
; X32-SSE-NEXT: popl %ebp
|
|
|
|
|
; X32-SSE-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X32-AVX-LABEL: f:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X32-AVX: # %bb.0:
|
2016-06-03 18:15:36 +08:00
|
|
|
; X32-AVX-NEXT: pushl %ebp
|
|
|
|
|
; X32-AVX-NEXT: movl %esp, %ebp
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-AVX-NEXT: pushl %esi
|
2016-06-03 18:15:36 +08:00
|
|
|
; X32-AVX-NEXT: andl $-16, %esp
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: subl $16, %esp
|
|
|
|
|
; X32-AVX-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-AVX-NEXT: movl 12(%ebp), %eax
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: vmovdqa 56(%ebp), %xmm4
|
|
|
|
|
; X32-AVX-NEXT: vmovdqa 40(%ebp), %xmm5
|
|
|
|
|
; X32-AVX-NEXT: vmovdqa 24(%ebp), %xmm6
|
|
|
|
|
; X32-AVX-NEXT: movl 8(%ebp), %ecx
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-AVX-NEXT: movl 80(%ebp), %edx
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: movl (%edx), %esi
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
; X32-AVX-NEXT: vaddps {{\.LCPI.*}}, %xmm0, %xmm0
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: vmovntps %xmm0, (%ecx)
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
; X32-AVX-NEXT: vpaddq {{\.LCPI.*}}, %xmm2, %xmm0
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: addl (%edx), %esi
|
|
|
|
|
; X32-AVX-NEXT: vmovntdq %xmm0, (%ecx)
|
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
|
|
|
; X32-AVX-NEXT: vaddpd {{\.LCPI.*}}, %xmm1, %xmm0
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: addl (%edx), %esi
|
|
|
|
|
; X32-AVX-NEXT: vmovntpd %xmm0, (%ecx)
|
|
|
|
|
; X32-AVX-NEXT: vpaddd {{\.LCPI.*}}, %xmm6, %xmm0
|
|
|
|
|
; X32-AVX-NEXT: addl (%edx), %esi
|
|
|
|
|
; X32-AVX-NEXT: vmovntdq %xmm0, (%ecx)
|
|
|
|
|
; X32-AVX-NEXT: vpaddw {{\.LCPI.*}}, %xmm5, %xmm0
|
|
|
|
|
; X32-AVX-NEXT: addl (%edx), %esi
|
|
|
|
|
; X32-AVX-NEXT: vmovntdq %xmm0, (%ecx)
|
|
|
|
|
; X32-AVX-NEXT: vpaddb {{\.LCPI.*}}, %xmm4, %xmm0
|
|
|
|
|
; X32-AVX-NEXT: addl (%edx), %esi
|
|
|
|
|
; X32-AVX-NEXT: vmovntdq %xmm0, (%ecx)
|
|
|
|
|
; X32-AVX-NEXT: addl (%edx), %esi
|
|
|
|
|
; X32-AVX-NEXT: movntil %eax, (%ecx)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-AVX-NEXT: movl (%edx), %eax
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: addl %esi, %eax
|
|
|
|
|
; X32-AVX-NEXT: vmovsd %xmm3, (%ecx)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-AVX-NEXT: addl (%edx), %eax
|
2017-12-13 02:25:48 +08:00
|
|
|
; X32-AVX-NEXT: leal -4(%ebp), %esp
|
2017-12-11 23:35:40 +08:00
|
|
|
; X32-AVX-NEXT: popl %esi
|
2016-06-03 18:15:36 +08:00
|
|
|
; X32-AVX-NEXT: popl %ebp
|
|
|
|
|
; X32-AVX-NEXT: retl
|
|
|
|
|
;
|
|
|
|
|
; X64-SSE-LABEL: f:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64-SSE: # %bb.0:
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: movl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: addps {{.*}}(%rip), %xmm0
|
|
|
|
|
; X64-SSE-NEXT: movntps %xmm0, (%rdi)
|
|
|
|
|
; X64-SSE-NEXT: paddq {{.*}}(%rip), %xmm2
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: movntdq %xmm2, (%rdi)
|
|
|
|
|
; X64-SSE-NEXT: addpd {{.*}}(%rip), %xmm1
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: movntpd %xmm1, (%rdi)
|
|
|
|
|
; X64-SSE-NEXT: paddd {{.*}}(%rip), %xmm3
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: movntdq %xmm3, (%rdi)
|
|
|
|
|
; X64-SSE-NEXT: paddw {{.*}}(%rip), %xmm4
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: movntdq %xmm4, (%rdi)
|
|
|
|
|
; X64-SSE-NEXT: paddb {{.*}}(%rip), %xmm5
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: movntdq %xmm5, (%rdi)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: movntil %esi, (%rdi)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: movntiq %rdx, (%rdi)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-SSE-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; X64-AVX-LABEL: f:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64-AVX: # %bb.0:
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: movl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
|
|
|
|
|
; X64-AVX-NEXT: vmovntps %xmm0, (%rdi)
|
|
|
|
|
; X64-AVX-NEXT: vpaddq {{.*}}(%rip), %xmm2, %xmm0
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
|
|
|
|
|
; X64-AVX-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm0
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: vmovntpd %xmm0, (%rdi)
|
|
|
|
|
; X64-AVX-NEXT: vpaddd {{.*}}(%rip), %xmm3, %xmm0
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
|
|
|
|
|
; X64-AVX-NEXT: vpaddw {{.*}}(%rip), %xmm4, %xmm0
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
|
|
|
|
|
; X64-AVX-NEXT: vpaddb {{.*}}(%rip), %xmm5, %xmm0
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: movntil %esi, (%rdi)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: movntiq %rdx, (%rdi)
|
2017-12-11 23:35:40 +08:00
|
|
|
; X64-AVX-NEXT: addl (%rcx), %eax
|
2016-06-03 18:15:36 +08:00
|
|
|
; X64-AVX-NEXT: retq
|
2017-12-11 23:35:40 +08:00
|
|
|
%v0 = load i32, i32* %loadptr, align 1
|
2011-05-04 05:11:17 +08:00
|
|
|
%cast = bitcast i8* %B to <4 x float>*
|
2016-06-03 18:15:36 +08:00
|
|
|
%A2 = fadd <4 x float> %A, <float 1.0, float 2.0, float 3.0, float 4.0>
|
2011-11-08 07:08:21 +08:00
|
|
|
store <4 x float> %A2, <4 x float>* %cast, align 16, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v1 = load i32, i32* %loadptr, align 1
|
2011-05-04 05:11:17 +08:00
|
|
|
%cast1 = bitcast i8* %B to <2 x i64>*
|
2011-11-08 07:08:21 +08:00
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%E2 = add <2 x i64> %E, <i64 1, i64 2>
|
|
|
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|
store <2 x i64> %E2, <2 x i64>* %cast1, align 16, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v2 = load i32, i32* %loadptr, align 1
|
2011-05-04 05:11:17 +08:00
|
|
|
%cast2 = bitcast i8* %B to <2 x double>*
|
2016-06-03 18:15:36 +08:00
|
|
|
%C2 = fadd <2 x double> %C, <double 1.0, double 2.0>
|
2011-11-08 07:08:21 +08:00
|
|
|
store <2 x double> %C2, <2 x double>* %cast2, align 16, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v3 = load i32, i32* %loadptr, align 1
|
2016-06-03 18:15:36 +08:00
|
|
|
%cast3 = bitcast i8* %B to <4 x i32>*
|
|
|
|
|
%F2 = add <4 x i32> %F, <i32 1, i32 2, i32 3, i32 4>
|
|
|
|
|
store <4 x i32> %F2, <4 x i32>* %cast3, align 16, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v4 = load i32, i32* %loadptr, align 1
|
2016-06-03 18:15:36 +08:00
|
|
|
%cast4 = bitcast i8* %B to <8 x i16>*
|
|
|
|
|
%G2 = add <8 x i16> %G, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
|
|
|
|
|
store <8 x i16> %G2, <8 x i16>* %cast4, align 16, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v5 = load i32, i32* %loadptr, align 1
|
2016-06-03 18:15:36 +08:00
|
|
|
%cast5 = bitcast i8* %B to <16 x i8>*
|
|
|
|
|
%H2 = add <16 x i8> %H, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
|
|
|
|
|
store <16 x i8> %H2, <16 x i8>* %cast5, align 16, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v6 = load i32, i32* %loadptr, align 1
|
2016-06-03 18:15:36 +08:00
|
|
|
%cast6 = bitcast i8* %B to i32*
|
|
|
|
|
store i32 %D, i32* %cast6, align 1, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v7 = load i32, i32* %loadptr, align 1
|
2016-06-03 18:15:36 +08:00
|
|
|
%cast7 = bitcast i8* %B to i64*
|
|
|
|
|
store i64 %I, i64* %cast7, align 1, !nontemporal !0
|
2017-12-11 23:35:40 +08:00
|
|
|
%v8 = load i32, i32* %loadptr, align 1
|
|
|
|
|
%sum1 = add i32 %v0, %v1
|
|
|
|
|
%sum2 = add i32 %sum1, %v2
|
|
|
|
|
%sum3 = add i32 %sum2, %v3
|
|
|
|
|
%sum4 = add i32 %sum3, %v4
|
|
|
|
|
%sum5 = add i32 %sum4, %v5
|
|
|
|
|
%sum6 = add i32 %sum5, %v6
|
|
|
|
|
%sum7 = add i32 %sum6, %v7
|
|
|
|
|
%sum8 = add i32 %sum7, %v8
|
|
|
|
|
ret i32 %sum8
|
2011-05-04 05:11:17 +08:00
|
|
|
}
|
|
|
|
|
|
IR: Make metadata typeless in assembly
Now that `Metadata` is typeless, reflect that in the assembly. These
are the matching assembly changes for the metadata/value split in
r223802.
- Only use the `metadata` type when referencing metadata from a call
intrinsic -- i.e., only when it's used as a `Value`.
- Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode`
when referencing it from call intrinsics.
So, assembly like this:
define @foo(i32 %v) {
call void @llvm.foo(metadata !{i32 %v}, metadata !0)
call void @llvm.foo(metadata !{i32 7}, metadata !0)
call void @llvm.foo(metadata !1, metadata !0)
call void @llvm.foo(metadata !3, metadata !0)
call void @llvm.foo(metadata !{metadata !3}, metadata !0)
ret void, !bar !2
}
!0 = metadata !{metadata !2}
!1 = metadata !{i32* @global}
!2 = metadata !{metadata !3}
!3 = metadata !{}
turns into this:
define @foo(i32 %v) {
call void @llvm.foo(metadata i32 %v, metadata !0)
call void @llvm.foo(metadata i32 7, metadata !0)
call void @llvm.foo(metadata i32* @global, metadata !0)
call void @llvm.foo(metadata !3, metadata !0)
call void @llvm.foo(metadata !{!3}, metadata !0)
ret void, !bar !2
}
!0 = !{!2}
!1 = !{i32* @global}
!2 = !{!3}
!3 = !{}
I wrote an upgrade script that handled almost all of the tests in llvm
and many of the tests in cfe (even handling many `CHECK` lines). I've
attached it (or will attach it in a moment if you're speedy) to PR21532
to help everyone update their out-of-tree testcases.
This is part of PR21532.
llvm-svn: 224257
2014-12-16 03:07:53 +08:00
|
|
|
!0 = !{i32 1}
|