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llvm-project/llvm/lib/Target/X86/X86ScheduleAtom.td

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the Intel Atom (Bonnell)
// processors.
//
//===----------------------------------------------------------------------===//
//
// Scheduling information derived from the "Intel 64 and IA32 Architectures
// Optimization Reference Manual", Chapter 13, Section 4.
// Functional Units
// Port 0
def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
// SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
// SIMD/FP: SIMD ALU, FP Adder
def AtomItineraries : ProcessorItineraries<
[ Port0, Port1 ],
[], [
// P0 only
// InstrItinData<class, [InstrStage<N, [P0]>] >,
// P0 or P1
// InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
// P0 and P1
// InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
//
// Default is 1 cycle, port0 or port1
InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
// mul
InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
// imul by al, ax, eax, rax
InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
// imul reg by reg|mem
InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
// imul reg = reg/mem * imm
InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
// idiv
InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
// div
InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
// neg/not/inc/dec
InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
// add/sub/and/or/xor/adc/sbc/cmp/test
InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >,
// shift/rotate
InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >,
// shift double
InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
// cmov
InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
// set
InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
// jcc
InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
// jcxz/jecxz/jrcxz
InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
// jmp rel
InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
// jmp indirect
InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
// jmp far
InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
// loop/loope/loopne
InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
// call - all but reg/imm
This patch adds instruction latencies for the SSE instructions to the instruction scheduler for the Intel Atom. llvm-svn: 151590
2012-02-28 07:35:03 +08:00
InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>,
InstrStage<1, [Port1]>] >,
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00
InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
//ret
InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
This patch adds instruction latencies for the SSE instructions to the instruction scheduler for the Intel Atom. llvm-svn: 151590
2012-02-28 07:35:03 +08:00
InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
Intel Atom instruction itineraries for mov sign extension and mov zero extension. Patch by Tyler Nowicki! llvm-svn: 151743
2012-03-01 03:44:41 +08:00
//sign extension movs
InstrItinData<IIC_MOVSX,[InstrStage<1, [Port0] >] >,
InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >,
//zero extension movs
InstrItinData<IIC_MOVZX,[InstrStage<1, [Port0]>] >,
InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
This patch adds X86 instruction itineraries for non-pseudo opcodes in X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. llvm-svn: 153033
2012-03-19 22:10:12 +08:00
InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >,
InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >,
This patch adds instruction latencies for the SSE instructions to the instruction scheduler for the Intel Atom. llvm-svn: 151590
2012-02-28 07:35:03 +08:00
// SSE binary operations
// arithmetic fp scalar
InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
InstrItinData<IIC_SSE_ALU_F32S_RM, [InstrStage<5, [Port0], 0>,
InstrStage<5, [Port1]>] >,
InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >,
InstrItinData<IIC_SSE_ALU_F64S_RM, [InstrStage<5, [Port0], 0>,
InstrStage<5, [Port1]>] >,
InstrItinData<IIC_SSE_MUL_F32S_RR, [InstrStage<4, [Port0]>] >,
InstrItinData<IIC_SSE_MUL_F32S_RM, [InstrStage<4, [Port0]>] >,
InstrItinData<IIC_SSE_MUL_F64S_RR, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_SSE_MUL_F64S_RM, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >,
// arithmetic fp parallel
InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >,
InstrItinData<IIC_SSE_ALU_F32P_RM, [InstrStage<5, [Port0], 0>,
InstrStage<5, [Port1]>] >,
InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MUL_F32P_RR, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_SSE_MUL_F32P_RM, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >,
// bitwise parallel
InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_BIT_P_RM, [InstrStage<1, [Port0]>] >,
// arithmetic int parallel
InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_INTALU_P_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >,
// multiply int parallel
InstrItinData<IIC_SSE_INTMUL_P_RR, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_SSE_INTMUL_P_RM, [InstrStage<5, [Port0]>] >,
// shift parallel
InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CMPP_RR, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CMPP_RM, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_PSHUF, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_SQRTP_RR, [InstrStage<13, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_SQRTP_RM, [InstrStage<14, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_SQRTS_RR, [InstrStage<11, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_SQRTS_RM, [InstrStage<12, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >,
InstrItinData<IIC_SSE_RCPS_RM, [InstrStage<4, [Port0]>] >,
InstrItinData<IIC_SSE_MOVMSK, [InstrStage<3, [Port0]>] >,
InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PINSRW, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PABS_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MOV_S_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_MOV_S_MR, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MOVA_P_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_MOVA_P_MR, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MOV_LH, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MOVDQ, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_MOVD_ToGP, [InstrStage<3, [Port0]>] >,
InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MOVNT, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_PREFETCH, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MFENCE, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_SFENCE, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_PSIGN_RM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [Port0]>] >,
InstrItinData<IIC_SSE_PALIGNR, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >,
// conversions
// to/from PD ...
InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
// to/from PS except to/from PD and PS2PI
InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
This patch adds X86 instruction itineraries for non-pseudo opcodes in X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. llvm-svn: 153033
2012-03-19 22:10:12 +08:00
InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >,
InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >,
InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
This patch continues the work of adding instruction latencies for X86 Atom, by providing the latencies for the instructions in X86InstrFPStack.td. llvm-svn: 155996
2012-05-03 00:03:35 +08:00
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_FILD, [InstrStage<5, [Port0], 0>, InstrStage<5, [Port1]>] >,
InstrItinData<IIC_FLD, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_FLD80, [InstrStage<4, [Port0, Port1]>] >,
InstrItinData<IIC_FST, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_FST80, [InstrStage<5, [Port0, Port1]>] >,
InstrItinData<IIC_FIST, [InstrStage<6, [Port0, Port1]>] >,
InstrItinData<IIC_FLDZ, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_FUCOM, [InstrStage<1, [Port1]>] >,
InstrItinData<IIC_FUCOMI, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_FCOMI, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_FNSTSW, [InstrStage<10, [Port0, Port1]>] >,
InstrItinData<IIC_FNSTCW, [InstrStage<8, [Port0, Port1]>] >,
InstrItinData<IIC_FLDCW, [InstrStage<5, [Port0, Port1]>] >,
InstrItinData<IIC_FNINIT, [InstrStage<63, [Port0, Port1]>] >,
InstrItinData<IIC_FFREE, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_FNCLEX, [InstrStage<25, [Port0, Port1]>] >,
InstrItinData<IIC_WAIT, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_FXAM, [InstrStage<1, [Port0]>] >,
InstrItinData<IIC_FNOP, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_FLDL, [InstrStage<10, [Port0, Port1]>] >,
InstrItinData<IIC_F2XM1, [InstrStage<99, [Port0, Port1]>] >,
InstrItinData<IIC_FYL2X, [InstrStage<146, [Port0, Port1]>] >,
InstrItinData<IIC_FPTAN, [InstrStage<168, [Port0, Port1]>] >,
InstrItinData<IIC_FPATAN, [InstrStage<183, [Port0, Port1]>] >,
InstrItinData<IIC_FXTRACT, [InstrStage<25, [Port0, Port1]>] >,
InstrItinData<IIC_FPREM1, [InstrStage<71, [Port0, Port1]>] >,
InstrItinData<IIC_FPSTP, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_FPREM, [InstrStage<55, [Port0, Port1]>] >,
InstrItinData<IIC_FYL2XP1, [InstrStage<147, [Port0, Port1]>] >,
InstrItinData<IIC_FSINCOS, [InstrStage<174, [Port0, Port1]>] >,
InstrItinData<IIC_FRNDINT, [InstrStage<46, [Port0, Port1]>] >,
InstrItinData<IIC_FSCALE, [InstrStage<77, [Port0, Port1]>] >,
InstrItinData<IIC_FCOMPP, [InstrStage<1, [Port1]>] >,
InstrItinData<IIC_FXSAVE, [InstrStage<140, [Port0, Port1]>] >,
InstrItinData<IIC_FXRSTOR, [InstrStage<141, [Port0, Port1]>] >,
InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >
This patch adds X86 instruction itineraries for non-pseudo opcodes in X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. llvm-svn: 153033
2012-03-19 22:10:12 +08:00
]>;
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00