2004-08-03 00:54:54 +08:00
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//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
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2012-02-18 20:03:15 +08:00
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//
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2004-08-03 00:54:54 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2012-02-18 20:03:15 +08:00
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//
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2004-08-03 00:54:54 +08:00
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//===----------------------------------------------------------------------===//
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2004-08-03 05:56:35 +08:00
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//===----------------------------------------------------------------------===//
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//
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// PowerPC instruction formats
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
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2005-10-20 03:51:16 +08:00
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: Instruction {
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2004-08-03 05:56:35 +08:00
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field bits<32> Inst;
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2005-04-19 13:05:22 +08:00
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bit PPC64 = 0; // Default value, override with isPPC64
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2004-08-03 05:56:35 +08:00
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2004-08-11 06:47:03 +08:00
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let Namespace = "PPC";
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2004-08-10 01:24:04 +08:00
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let Inst{0-5} = opcode;
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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let OutOperandList = OOL;
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let InOperandList = IOL;
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2004-09-04 13:00:00 +08:00
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let AsmString = asmstr;
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2005-10-20 03:51:16 +08:00
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let Itinerary = itin;
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2010-04-05 11:10:20 +08:00
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2006-03-12 17:13:49 +08:00
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bits<1> PPC970_First = 0;
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bits<1> PPC970_Single = 0;
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2006-03-13 13:15:10 +08:00
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bits<1> PPC970_Cracked = 0;
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2006-03-12 17:13:49 +08:00
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bits<3> PPC970_Unit = 0;
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2010-04-05 11:10:20 +08:00
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/// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
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/// these must be reflected there! See comments there for what these are.
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let TSFlags{0} = PPC970_First;
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let TSFlags{1} = PPC970_Single;
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let TSFlags{2} = PPC970_Cracked;
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let TSFlags{5-3} = PPC970_Unit;
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2004-08-03 05:56:35 +08:00
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}
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2004-08-03 00:54:54 +08:00
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2006-03-13 13:15:10 +08:00
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class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
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class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
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class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
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2006-03-12 17:13:49 +08:00
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class PPC970_MicroCode;
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class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
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class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
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class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
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class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
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class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
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class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
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class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
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class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
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2012-03-31 22:45:15 +08:00
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// Two joined instructions; used to emit two adjacent instructions as one.
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// The itinerary from the first instruction is used for scheduling and
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// classification.
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class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin>
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: Instruction {
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field bits<64> Inst;
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bit PPC64 = 0; // Default value, override with isPPC64
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let Namespace = "PPC";
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let Inst{0-5} = opcode1;
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let Inst{32-37} = opcode2;
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let OutOperandList = OOL;
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let InOperandList = IOL;
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let AsmString = asmstr;
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let Itinerary = itin;
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bits<1> PPC970_First = 0;
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bits<1> PPC970_Single = 0;
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bits<1> PPC970_Cracked = 0;
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bits<3> PPC970_Unit = 0;
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/// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
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/// these must be reflected there! See comments there for what these are.
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let TSFlags{0} = PPC970_First;
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let TSFlags{1} = PPC970_Single;
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let TSFlags{2} = PPC970_Cracked;
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let TSFlags{5-3} = PPC970_Unit;
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}
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2006-03-12 17:13:49 +08:00
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2004-08-10 01:24:04 +08:00
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// 1.7.1 I-Form
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
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2005-12-05 02:42:54 +08:00
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InstrItinClass itin, list<dag> pattern>
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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: I<opcode, OOL, IOL, asmstr, itin> {
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2005-12-05 02:42:54 +08:00
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let Pattern = pattern;
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2004-10-14 13:55:37 +08:00
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bits<24> LI;
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2004-08-03 05:56:35 +08:00
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2004-08-10 01:24:04 +08:00
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let Inst{6-29} = LI;
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let Inst{30} = aa;
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let Inst{31} = lk;
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2004-08-03 05:56:35 +08:00
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}
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2004-08-03 00:54:54 +08:00
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2004-08-10 01:24:04 +08:00
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// 1.7.2 B-Form
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
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: I<opcode, OOL, IOL, asmstr, BrB> {
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2006-11-18 07:53:28 +08:00
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bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
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bits<3> CR;
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bits<14> BD;
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bits<5> BI;
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let BI{0-1} = BIBO{5-6};
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let BI{2-4} = CR{0-2};
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let Inst{6-10} = BIBO{4-0};
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let Inst{11-15} = BI;
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let Inst{16-29} = BD;
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let Inst{30} = aa;
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let Inst{31} = lk;
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}
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2004-08-10 01:24:04 +08:00
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// 1.7.4 D-Form
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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2004-10-14 13:55:37 +08:00
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bits<5> A;
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bits<5> B;
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bits<16> C;
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2005-12-10 07:54:18 +08:00
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let Pattern = pattern;
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2004-08-03 05:56:35 +08:00
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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}
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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2004-10-23 14:08:38 +08:00
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bits<5> A;
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split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
llvm-svn: 119134
2010-11-15 16:22:03 +08:00
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bits<21> Addr;
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let Pattern = pattern;
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let Inst{6-10} = A;
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let Inst{11-15} = Addr{20-16}; // Base Reg
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let Inst{16-31} = Addr{15-0}; // Displacement
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}
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class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<5> A;
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2004-10-23 14:08:38 +08:00
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bits<16> C;
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bits<5> B;
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2005-12-10 07:54:18 +08:00
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let Pattern = pattern;
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2004-10-23 14:08:38 +08:00
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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2004-08-03 05:56:35 +08:00
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}
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split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
llvm-svn: 119134
2010-11-15 16:22:03 +08:00
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>;
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2004-08-03 05:56:35 +08:00
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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2004-10-14 13:55:37 +08:00
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bits<5> A;
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bits<16> B;
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2004-09-04 13:00:00 +08:00
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2005-09-09 01:33:10 +08:00
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let Pattern = pattern;
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2004-09-04 13:00:00 +08:00
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let Inst{6-10} = A;
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let Inst{11-15} = 0;
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let Inst{16-31} = B;
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2004-08-03 00:54:54 +08:00
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}
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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2004-11-24 10:15:41 +08:00
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bits<5> B;
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bits<5> A;
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bits<16> C;
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2005-09-09 01:40:49 +08:00
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let Pattern = pattern;
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2004-11-24 10:15:41 +08:00
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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}
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2004-09-04 13:00:00 +08:00
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|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin, list<dag> pattern>
|
|
|
|
: DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let A = 0;
|
split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
llvm-svn: 119134
2010-11-15 16:22:03 +08:00
|
|
|
let Addr = 0;
|
2004-08-03 05:56:35 +08:00
|
|
|
}
|
|
|
|
|
2012-03-31 22:45:15 +08:00
|
|
|
class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
|
|
|
|
dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin, list<dag> pattern>
|
|
|
|
: I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
|
|
|
|
bits<5> A;
|
|
|
|
bits<21> Addr;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
|
|
|
bits<24> LI;
|
|
|
|
|
|
|
|
let Inst{6-29} = LI;
|
|
|
|
let Inst{30} = aa;
|
|
|
|
let Inst{31} = lk;
|
|
|
|
|
|
|
|
let Inst{38-42} = A;
|
|
|
|
let Inst{43-47} = Addr{20-16}; // Base Reg
|
|
|
|
let Inst{48-63} = Addr{15-0}; // Displacement
|
|
|
|
}
|
|
|
|
|
|
|
|
// This is used to emit BL8+NOP.
|
|
|
|
class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
|
|
|
|
dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin, list<dag> pattern>
|
|
|
|
: IForm_and_DForm_1<opcode1, aa, lk, opcode2,
|
|
|
|
OOL, IOL, asmstr, itin, pattern> {
|
|
|
|
let A = 0;
|
|
|
|
let Addr = 0;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin>
|
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<3> BF;
|
|
|
|
bits<1> L;
|
|
|
|
bits<5> RA;
|
|
|
|
bits<16> I;
|
2004-08-10 01:24:04 +08:00
|
|
|
|
|
|
|
let Inst{6-8} = BF;
|
|
|
|
let Inst{9} = 0;
|
|
|
|
let Inst{10} = L;
|
|
|
|
let Inst{11-15} = RA;
|
|
|
|
let Inst{16-31} = I;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin>
|
|
|
|
: DForm_5<opcode, OOL, IOL, asmstr, itin> {
|
2005-04-19 12:59:28 +08:00
|
|
|
let L = PPC64;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin>
|
|
|
|
: DForm_5<opcode, OOL, IOL, asmstr, itin>;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin>
|
|
|
|
: DForm_6<opcode, OOL, IOL, asmstr, itin> {
|
2005-04-19 12:59:28 +08:00
|
|
|
let L = PPC64;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2004-08-11 23:54:36 +08:00
|
|
|
// 1.7.5 DS-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
|
2005-12-10 07:54:18 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> RST;
|
2010-11-15 16:02:41 +08:00
|
|
|
bits<19> DS_RA;
|
2004-08-11 23:54:36 +08:00
|
|
|
|
2005-12-10 07:54:18 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2004-08-11 23:54:36 +08:00
|
|
|
let Inst{6-10} = RST;
|
2010-11-15 16:02:41 +08:00
|
|
|
let Inst{11-15} = DS_RA{18-14}; // Register #
|
|
|
|
let Inst{16-29} = DS_RA{13-0}; // Displacement.
|
2004-08-11 23:54:36 +08:00
|
|
|
let Inst{30-31} = xo;
|
|
|
|
}
|
|
|
|
|
2010-11-15 16:02:41 +08:00
|
|
|
class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin, list<dag> pattern>
|
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
|
|
|
bits<5> RST;
|
|
|
|
bits<14> DS;
|
|
|
|
bits<5> RA;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
|
|
|
|
|
|
|
let Inst{6-10} = RST;
|
|
|
|
let Inst{11-15} = RA;
|
|
|
|
let Inst{16-29} = DS;
|
|
|
|
let Inst{30-31} = xo;
|
|
|
|
}
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
// 1.7.6 X-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-12-10 07:54:18 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> RST;
|
|
|
|
bits<5> A;
|
|
|
|
bits<5> B;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2005-12-10 07:54:18 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2005-04-19 13:15:18 +08:00
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
2004-08-11 23:54:36 +08:00
|
|
|
let Inst{6-10} = RST;
|
2004-08-10 01:24:04 +08:00
|
|
|
let Inst{11-15} = A;
|
|
|
|
let Inst{16-20} = B;
|
|
|
|
let Inst{21-30} = xo;
|
2005-04-19 13:15:18 +08:00
|
|
|
let Inst{31} = RC;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
2004-11-24 11:52:02 +08:00
|
|
|
// This is the same as XForm_base_r3xo, but the first two operands are swapped
|
|
|
|
// when code is emitted.
|
|
|
|
class XForm_base_r3xo_swapped
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-11-24 11:52:02 +08:00
|
|
|
bits<5> A;
|
|
|
|
bits<5> RST;
|
|
|
|
bits<5> B;
|
|
|
|
|
2005-04-19 13:15:18 +08:00
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
2004-11-24 11:52:02 +08:00
|
|
|
let Inst{6-10} = RST;
|
|
|
|
let Inst{11-15} = A;
|
|
|
|
let Inst{16-20} = B;
|
|
|
|
let Inst{21-30} = xo;
|
2005-04-19 13:15:18 +08:00
|
|
|
let Inst{31} = RC;
|
2004-11-24 11:52:02 +08:00
|
|
|
}
|
|
|
|
|
2004-08-13 10:19:26 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-12-10 07:54:18 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
|
2005-09-03 06:35:53 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-12-10 07:54:18 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
|
2005-10-20 03:51:16 +08:00
|
|
|
let Pattern = pattern;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let B = 0;
|
2005-09-03 06:35:53 +08:00
|
|
|
let Pattern = pattern;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<3> BF;
|
|
|
|
bits<1> L;
|
|
|
|
bits<5> RA;
|
|
|
|
bits<5> RB;
|
2004-08-10 01:24:04 +08:00
|
|
|
|
|
|
|
let Inst{6-8} = BF;
|
|
|
|
let Inst{9} = 0;
|
|
|
|
let Inst{10} = L;
|
|
|
|
let Inst{11-15} = RA;
|
|
|
|
let Inst{16-20} = RB;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
|
2005-04-19 12:51:30 +08:00
|
|
|
let L = PPC64;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<3> BF;
|
|
|
|
bits<5> FRA;
|
|
|
|
bits<5> FRB;
|
2004-08-10 01:24:04 +08:00
|
|
|
|
|
|
|
let Inst{6-8} = BF;
|
|
|
|
let Inst{9-10} = 0;
|
|
|
|
let Inst{11-15} = FRA;
|
|
|
|
let Inst{16-20} = FRB;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2008-08-12 01:36:31 +08:00
|
|
|
class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin, list<dag> pattern>
|
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
|
|
|
let Pattern = pattern;
|
|
|
|
let Inst{6-10} = 31;
|
|
|
|
let Inst{11-15} = 0;
|
|
|
|
let Inst{16-20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
2008-08-23 01:20:54 +08:00
|
|
|
class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
|
|
|
|
string asmstr, InstrItinClass itin, list<dag> pattern>
|
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
|
|
|
let Pattern = pattern;
|
|
|
|
let Inst{6-10} = 0;
|
|
|
|
let Inst{11-15} = 0;
|
|
|
|
let Inst{16-20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-12-10 07:54:18 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let A = 0;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-12-10 07:54:18 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2007-10-10 09:01:31 +08:00
|
|
|
// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
|
|
|
|
// numbers presumably relates to some document, but I haven't found it.
|
|
|
|
class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin, list<dag> pattern>
|
|
|
|
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
|
|
|
|
let Pattern = pattern;
|
|
|
|
|
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
|
|
|
let Inst{6-10} = RST;
|
|
|
|
let Inst{11-20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = RC;
|
|
|
|
}
|
|
|
|
class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
|
|
|
InstrItinClass itin, list<dag> pattern>
|
|
|
|
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
|
|
|
|
let Pattern = pattern;
|
|
|
|
bits<5> FM;
|
|
|
|
|
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
|
|
|
let Inst{6-10} = FM;
|
|
|
|
let Inst{11-20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = RC;
|
|
|
|
}
|
|
|
|
|
2006-06-07 05:29:23 +08:00
|
|
|
// DCB_Form - Form X instruction, used for dcb* instructions.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
|
2006-06-07 05:29:23 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<31, OOL, IOL, asmstr, itin> {
|
2006-06-07 05:29:23 +08:00
|
|
|
bits<5> A;
|
|
|
|
bits<5> B;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
|
|
|
|
|
|
|
let Inst{6-10} = immfield;
|
|
|
|
let Inst{11-15} = A;
|
|
|
|
let Inst{16-20} = B;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-04-06 06:27:14 +08:00
|
|
|
// DSS_Form - Form X instruction, used for altivec dss* instructions.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2006-04-06 06:27:14 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<31, OOL, IOL, asmstr, itin> {
|
2006-04-06 06:27:14 +08:00
|
|
|
bits<1> T;
|
|
|
|
bits<2> STRM;
|
|
|
|
bits<5> A;
|
|
|
|
bits<5> B;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
|
|
|
|
|
|
|
let Inst{6} = T;
|
|
|
|
let Inst{7-8} = 0;
|
|
|
|
let Inst{9-10} = STRM;
|
|
|
|
let Inst{11-15} = A;
|
|
|
|
let Inst{16-20} = B;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
// 1.7.7 XL-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2007-02-25 13:07:49 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2007-02-25 13:07:49 +08:00
|
|
|
bits<5> CRD;
|
|
|
|
bits<5> CRA;
|
|
|
|
bits<5> CRB;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
|
|
|
|
|
|
|
let Inst{6-10} = CRD;
|
|
|
|
let Inst{11-15} = CRA;
|
|
|
|
let Inst{16-20} = CRB;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2007-02-25 13:07:49 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2007-02-25 13:07:49 +08:00
|
|
|
bits<5> CRD;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
2005-04-14 11:20:38 +08:00
|
|
|
|
2007-02-25 13:07:49 +08:00
|
|
|
let Inst{6-10} = CRD;
|
|
|
|
let Inst{11-15} = CRD;
|
|
|
|
let Inst{16-20} = CRD;
|
2005-04-14 11:20:38 +08:00
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
|
2005-12-20 08:26:01 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> BO;
|
|
|
|
bits<5> BI;
|
|
|
|
bits<2> BH;
|
2004-08-10 01:24:04 +08:00
|
|
|
|
2005-12-20 08:26:01 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
let Inst{6-10} = BO;
|
|
|
|
let Inst{11-15} = BI;
|
|
|
|
let Inst{16-18} = 0;
|
|
|
|
let Inst{19-20} = BH;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = lk;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2006-11-04 13:42:48 +08:00
|
|
|
class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
|
|
|
|
: XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
|
2006-11-04 13:42:48 +08:00
|
|
|
bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
|
|
|
|
bits<3> CR;
|
|
|
|
|
2006-11-07 09:51:50 +08:00
|
|
|
let BO = BIBO{2-6};
|
|
|
|
let BI{0-1} = BIBO{0-1};
|
2006-11-04 13:42:48 +08:00
|
|
|
let BI{2-4} = CR;
|
|
|
|
let BH = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-10-20 03:51:16 +08:00
|
|
|
class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
|
|
|
|
: XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let BO = bo;
|
|
|
|
let BI = bi;
|
|
|
|
let BH = 0;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2005-04-12 15:04:16 +08:00
|
|
|
bits<3> BF;
|
|
|
|
bits<3> BFA;
|
|
|
|
|
|
|
|
let Inst{6-8} = BF;
|
|
|
|
let Inst{9-10} = 0;
|
|
|
|
let Inst{11-13} = BFA;
|
|
|
|
let Inst{14-15} = 0;
|
|
|
|
let Inst{16-20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
// 1.7.8 XFX-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2005-04-12 15:04:16 +08:00
|
|
|
bits<5> RT;
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<10> SPR;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2005-04-12 15:04:16 +08:00
|
|
|
let Inst{6-10} = RT;
|
2005-11-30 06:42:50 +08:00
|
|
|
let Inst{11} = SPR{4};
|
|
|
|
let Inst{12} = SPR{3};
|
|
|
|
let Inst{13} = SPR{2};
|
|
|
|
let Inst{14} = SPR{1};
|
|
|
|
let Inst{15} = SPR{0};
|
|
|
|
let Inst{16} = SPR{9};
|
|
|
|
let Inst{17} = SPR{8};
|
|
|
|
let Inst{18} = SPR{7};
|
|
|
|
let Inst{19} = SPR{6};
|
|
|
|
let Inst{20} = SPR{5};
|
2004-08-10 01:24:04 +08:00
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
2005-04-19 12:40:07 +08:00
|
|
|
class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
dag OOL, dag IOL, string asmstr, InstrItinClass itin>
|
|
|
|
: XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let SPR = spr;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2005-04-12 15:04:16 +08:00
|
|
|
bits<5> RT;
|
|
|
|
|
|
|
|
let Inst{6-10} = RT;
|
|
|
|
let Inst{11-20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2005-04-12 15:04:16 +08:00
|
|
|
bits<8> FXM;
|
|
|
|
bits<5> ST;
|
|
|
|
|
|
|
|
let Inst{6-10} = ST;
|
2005-08-09 04:04:52 +08:00
|
|
|
let Inst{11} = 0;
|
2005-04-12 15:04:16 +08:00
|
|
|
let Inst{12-19} = FXM;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2005-08-09 04:04:52 +08:00
|
|
|
bits<5> ST;
|
|
|
|
bits<8> FXM;
|
|
|
|
|
|
|
|
let Inst{6-10} = ST;
|
|
|
|
let Inst{11} = 1;
|
|
|
|
let Inst{12-19} = FXM;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = 0;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2004-08-30 10:28:06 +08:00
|
|
|
class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
dag OOL, dag IOL, string asmstr, InstrItinClass itin>
|
|
|
|
: XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let SPR = spr;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
2007-10-10 09:01:31 +08:00
|
|
|
// XFL-Form - MTFSF
|
|
|
|
// This is probably 1.7.9, but I don't have the reference that uses this
|
|
|
|
// numbering scheme...
|
|
|
|
class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
|
|
|
|
string cstr, InstrItinClass itin, list<dag>pattern>
|
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
|
|
|
bits<8> FM;
|
|
|
|
bits<5> RT;
|
|
|
|
|
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
let Pattern = pattern;
|
|
|
|
let Constraints = cstr;
|
|
|
|
|
|
|
|
let Inst{6} = 0;
|
|
|
|
let Inst{7-14} = FM;
|
|
|
|
let Inst{15} = 0;
|
|
|
|
let Inst{16-20} = RT;
|
|
|
|
let Inst{21-30} = xo;
|
|
|
|
let Inst{31} = RC;
|
|
|
|
}
|
|
|
|
|
2006-12-07 04:02:54 +08:00
|
|
|
// 1.7.10 XS-Form - SRADI.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
|
2006-06-28 04:07:26 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> A;
|
2006-12-07 05:35:10 +08:00
|
|
|
bits<5> RS;
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<6> SH;
|
2004-08-13 10:19:26 +08:00
|
|
|
|
2005-04-19 13:15:18 +08:00
|
|
|
bit RC = 0; // set by isDOT
|
2006-06-28 04:07:26 +08:00
|
|
|
let Pattern = pattern;
|
2005-04-19 13:15:18 +08:00
|
|
|
|
2004-08-13 10:19:26 +08:00
|
|
|
let Inst{6-10} = RS;
|
|
|
|
let Inst{11-15} = A;
|
2006-12-07 04:02:54 +08:00
|
|
|
let Inst{16-20} = SH{4,3,2,1,0};
|
2004-08-13 10:19:26 +08:00
|
|
|
let Inst{21-29} = xo;
|
2006-12-07 04:02:54 +08:00
|
|
|
let Inst{30} = SH{5};
|
2005-04-19 13:15:18 +08:00
|
|
|
let Inst{31} = RC;
|
2004-08-13 10:19:26 +08:00
|
|
|
}
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
// 1.7.11 XO-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> RT;
|
|
|
|
bits<5> RA;
|
|
|
|
bits<5> RB;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2005-09-03 05:18:00 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2005-04-19 13:21:30 +08:00
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
let Inst{6-10} = RT;
|
|
|
|
let Inst{11-15} = RA;
|
|
|
|
let Inst{16-20} = RB;
|
|
|
|
let Inst{21} = oe;
|
|
|
|
let Inst{22-30} = xo;
|
2005-04-19 13:21:30 +08:00
|
|
|
let Inst{31} = RC;
|
2004-08-10 01:24:04 +08:00
|
|
|
}
|
|
|
|
|
2005-04-19 13:21:30 +08:00
|
|
|
class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
|
|
|
|
: XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let RB = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// 1.7.12 A-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> FRT;
|
|
|
|
bits<5> FRA;
|
|
|
|
bits<5> FRC;
|
2004-11-25 12:11:07 +08:00
|
|
|
bits<5> FRB;
|
2004-08-10 01:24:04 +08:00
|
|
|
|
2005-09-30 07:34:24 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2005-04-19 13:21:30 +08:00
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
let Inst{6-10} = FRT;
|
|
|
|
let Inst{11-15} = FRA;
|
|
|
|
let Inst{16-20} = FRB;
|
|
|
|
let Inst{21-25} = FRC;
|
|
|
|
let Inst{26-30} = xo;
|
2005-04-19 13:21:30 +08:00
|
|
|
let Inst{31} = RC;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let FRC = 0;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
let FRB = 0;
|
|
|
|
}
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
// 1.7.13 M-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> RA;
|
2004-11-24 03:23:32 +08:00
|
|
|
bits<5> RS;
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> RB;
|
|
|
|
bits<5> MB;
|
|
|
|
bits<5> ME;
|
2004-08-03 00:54:54 +08:00
|
|
|
|
2005-10-20 02:42:01 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2005-04-19 13:21:30 +08:00
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
2004-08-10 01:24:04 +08:00
|
|
|
let Inst{6-10} = RS;
|
|
|
|
let Inst{11-15} = RA;
|
|
|
|
let Inst{16-20} = RB;
|
|
|
|
let Inst{21-25} = MB;
|
|
|
|
let Inst{26-30} = ME;
|
2005-04-19 13:21:30 +08:00
|
|
|
let Inst{31} = RC;
|
2004-08-03 00:54:54 +08:00
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
|
2004-08-10 01:24:04 +08:00
|
|
|
}
|
|
|
|
|
2004-08-13 10:19:26 +08:00
|
|
|
// 1.7.14 MD-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
|
2005-10-20 03:51:16 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<opcode, OOL, IOL, asmstr, itin> {
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<5> RA;
|
2006-07-14 05:52:41 +08:00
|
|
|
bits<5> RS;
|
2004-10-14 13:55:37 +08:00
|
|
|
bits<6> SH;
|
|
|
|
bits<6> MBE;
|
2004-08-13 10:19:26 +08:00
|
|
|
|
2005-10-20 02:42:01 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2005-04-19 13:21:30 +08:00
|
|
|
bit RC = 0; // set by isDOT
|
|
|
|
|
2004-08-13 10:19:26 +08:00
|
|
|
let Inst{6-10} = RS;
|
|
|
|
let Inst{11-15} = RA;
|
2006-12-07 04:02:54 +08:00
|
|
|
let Inst{16-20} = SH{4,3,2,1,0};
|
|
|
|
let Inst{21-26} = MBE{4,3,2,1,0,5};
|
2004-08-13 10:19:26 +08:00
|
|
|
let Inst{27-29} = xo;
|
2006-07-13 06:08:13 +08:00
|
|
|
let Inst{30} = SH{5};
|
2005-04-19 13:21:30 +08:00
|
|
|
let Inst{31} = RC;
|
2004-08-13 10:19:26 +08:00
|
|
|
}
|
|
|
|
|
2006-04-06 06:27:14 +08:00
|
|
|
|
|
|
|
|
2005-11-23 13:29:52 +08:00
|
|
|
// E-1 VA-Form
|
2006-03-27 11:34:17 +08:00
|
|
|
|
|
|
|
// VAForm_1 - DACB ordering.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
|
2005-11-23 13:29:52 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<4, OOL, IOL, asmstr, itin> {
|
2005-11-23 13:29:52 +08:00
|
|
|
bits<5> VD;
|
|
|
|
bits<5> VA;
|
|
|
|
bits<5> VC;
|
2006-03-22 09:44:36 +08:00
|
|
|
bits<5> VB;
|
2005-11-27 06:39:34 +08:00
|
|
|
|
|
|
|
let Pattern = pattern;
|
2005-11-23 13:29:52 +08:00
|
|
|
|
|
|
|
let Inst{6-10} = VD;
|
|
|
|
let Inst{11-15} = VA;
|
|
|
|
let Inst{16-20} = VB;
|
|
|
|
let Inst{21-25} = VC;
|
|
|
|
let Inst{26-31} = xo;
|
|
|
|
}
|
|
|
|
|
2006-03-27 11:34:17 +08:00
|
|
|
// VAForm_1a - DABC ordering.
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
|
2006-03-27 11:34:17 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<4, OOL, IOL, asmstr, itin> {
|
2006-03-27 11:34:17 +08:00
|
|
|
bits<5> VD;
|
|
|
|
bits<5> VA;
|
|
|
|
bits<5> VB;
|
|
|
|
bits<5> VC;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
|
|
|
|
|
|
|
let Inst{6-10} = VD;
|
|
|
|
let Inst{11-15} = VA;
|
|
|
|
let Inst{16-20} = VB;
|
|
|
|
let Inst{21-25} = VC;
|
|
|
|
let Inst{26-31} = xo;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
|
2006-03-26 08:41:48 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<4, OOL, IOL, asmstr, itin> {
|
2006-03-26 08:41:48 +08:00
|
|
|
bits<5> VD;
|
|
|
|
bits<5> VA;
|
|
|
|
bits<5> VB;
|
|
|
|
bits<4> SH;
|
|
|
|
|
|
|
|
let Pattern = pattern;
|
|
|
|
|
|
|
|
let Inst{6-10} = VD;
|
|
|
|
let Inst{11-15} = VA;
|
|
|
|
let Inst{16-20} = VB;
|
|
|
|
let Inst{21} = 0;
|
|
|
|
let Inst{22-25} = SH;
|
|
|
|
let Inst{26-31} = xo;
|
|
|
|
}
|
|
|
|
|
2005-11-23 13:29:52 +08:00
|
|
|
// E-2 VX-Form
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
|
2005-11-23 13:29:52 +08:00
|
|
|
InstrItinClass itin, list<dag> pattern>
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
: I<4, OOL, IOL, asmstr, itin> {
|
2005-11-23 13:29:52 +08:00
|
|
|
bits<5> VD;
|
|
|
|
bits<5> VA;
|
|
|
|
bits<5> VB;
|
|
|
|
|
2005-11-27 06:39:34 +08:00
|
|
|
let Pattern = pattern;
|
|
|
|
|
2005-11-23 13:29:52 +08:00
|
|
|
let Inst{6-10} = VD;
|
|
|
|
let Inst{11-15} = VA;
|
|
|
|
let Inst{16-20} = VB;
|
|
|
|
let Inst{21-31} = xo;
|
|
|
|
}
|
|
|
|
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
|
Add support for fmul node of type v4f32.
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 08:34:09 +08:00
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InstrItinClass itin, list<dag> pattern>
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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: VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
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Add support for fmul node of type v4f32.
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 08:34:09 +08:00
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let VA = VD;
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let VB = VD;
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}
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
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2005-11-29 16:04:45 +08:00
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InstrItinClass itin, list<dag> pattern>
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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: I<4, OOL, IOL, asmstr, itin> {
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2005-11-29 16:04:45 +08:00
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bits<5> VD;
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bits<5> VB;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = 0;
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let Inst{16-20} = VB;
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let Inst{21-31} = xo;
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}
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
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2006-03-27 11:28:57 +08:00
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InstrItinClass itin, list<dag> pattern>
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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: I<4, OOL, IOL, asmstr, itin> {
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2006-03-27 11:28:57 +08:00
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bits<5> VD;
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bits<5> IMM;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = IMM;
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let Inst{16-20} = 0;
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let Inst{21-31} = xo;
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}
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2006-04-05 08:03:57 +08:00
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/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
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2006-04-05 08:03:57 +08:00
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InstrItinClass itin, list<dag> pattern>
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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: I<4, OOL, IOL, asmstr, itin> {
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2006-04-05 08:03:57 +08:00
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bits<5> VD;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = 0;
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let Inst{16-20} = 0;
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let Inst{21-31} = xo;
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}
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/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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2006-04-05 08:03:57 +08:00
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InstrItinClass itin, list<dag> pattern>
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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: I<4, OOL, IOL, asmstr, itin> {
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2006-04-05 08:03:57 +08:00
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bits<5> VB;
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let Pattern = pattern;
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let Inst{6-10} = 0;
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let Inst{11-15} = 0;
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let Inst{16-20} = VB;
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let Inst{21-31} = xo;
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}
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2006-03-27 11:28:57 +08:00
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2005-11-23 13:29:52 +08:00
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// E-4 VXR-Form
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
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2005-11-23 13:29:52 +08:00
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InstrItinClass itin, list<dag> pattern>
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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: I<4, OOL, IOL, asmstr, itin> {
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2005-11-23 13:29:52 +08:00
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bits<5> VD;
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bits<5> VA;
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bits<5> VB;
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2006-03-26 12:57:17 +08:00
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bit RC = 0;
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2005-11-23 13:29:52 +08:00
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2005-11-27 06:39:34 +08:00
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let Pattern = pattern;
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2005-11-23 13:29:52 +08:00
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = VB;
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2006-03-26 12:57:17 +08:00
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let Inst{21} = RC;
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2005-11-23 13:29:52 +08:00
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let Inst{22-31} = xo;
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}
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2004-08-10 01:24:04 +08:00
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//===----------------------------------------------------------------------===//
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
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: I<0, OOL, IOL, asmstr, NoItinerary> {
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2004-09-02 16:13:00 +08:00
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let PPC64 = 0;
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2005-10-26 04:58:43 +08:00
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let Pattern = pattern;
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2004-09-02 16:13:00 +08:00
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let Inst{31-0} = 0;
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2004-08-03 00:54:54 +08:00
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}
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