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llvm-project/llvm/test/CodeGen/PowerPC/pr32063.ll

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[PPC] Fix code generation for bswap(int32) followed by store16 This patch fixes pr32063. Current code in PPCTargetLowering::PerformDAGCombine can transform bswap store into a single PPCISD::STBRX instruction. but it doesn't consider the case that the operand size of bswap may be larger than store size. When it occurs, we need 2 modifications, 1 For the last operand of PPCISD::STBRX, we should not use DAG.getValueType(N->getOperand(1).getValueType()), instead we should use cast<StoreSDNode>(N)->getMemoryVT(). 2 Before PPCISD::STBRX, we need to shift the original operand of bswap to the right side. Differential Revision: https://reviews.llvm.org/D30362 llvm-svn: 296811
2017-03-03 05:07:59 +08:00
; RUN: llc -O2 < %s | FileCheck %s
target triple = "powerpc64le-linux-gnu"
define void @foo(i32 %v, i16* %p) {
%1 = and i32 %v, -65536
%2 = tail call i32 @llvm.bswap.i32(i32 %1)
%conv = trunc i32 %2 to i16
store i16 %conv, i16* %p
ret void
; CHECK: srwi
; CHECK: sthbrx
; CHECK-NOT: stwbrx
}
declare i32 @llvm.bswap.i32(i32)