2015-08-12 20:45:16 +08:00
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//=- MicroMips64r6InstrInfo.td - Instruction Information -*- tablegen -*- -=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes MicroMips64r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class DAUI_MMR6_ENC : DAUI_FM_MMR6;
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class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
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class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
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class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
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class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
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class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
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class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
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2015-08-18 22:40:43 +08:00
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class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
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class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
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class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
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class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
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2016-02-25 20:53:29 +08:00
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class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>;
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class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
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class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
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2016-03-24 16:02:09 +08:00
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class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
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class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
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class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
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2016-03-31 16:51:24 +08:00
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class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
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class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
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class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
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2016-04-08 15:27:26 +08:00
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class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
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class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
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class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
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2016-04-21 22:32:12 +08:00
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class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
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2016-04-27 19:31:44 +08:00
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class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
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class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
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2015-08-12 20:45:16 +08:00
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rt);
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dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
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list<dag> Pattern = [];
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}
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class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
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class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
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string Constraints = "$rs = $rt";
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}
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class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
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class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
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class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
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Operand SizeOpnd, SDPatternOperator Op = null_frag>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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2015-08-12 20:45:16 +08:00
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dag OutOperandList = (outs RO:$rt);
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2015-12-21 21:08:58 +08:00
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dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
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2015-08-12 20:45:16 +08:00
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string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
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list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
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InstrItinClass Itinerary = II_EXT;
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Format Form = FrmR;
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string BaseOpcode = instr_asm;
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}
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2015-12-21 21:08:58 +08:00
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// TODO: Add 'pos + size' constraint check to dext* instructions
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// DEXT: 0 < pos + size <= 63
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// DEXTM, DEXTU: 32 < pos + size <= 64
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2016-02-29 23:26:54 +08:00
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class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
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2015-12-21 21:08:58 +08:00
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uimm5_plus1, MipsExt>;
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2015-12-08 21:49:19 +08:00
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class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
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2015-12-21 21:08:58 +08:00
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uimm5_plus33, MipsExt>;
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2015-12-08 21:49:19 +08:00
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class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
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uimm5_plus1, MipsExt>;
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2015-08-12 20:45:16 +08:00
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class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
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list<dag> Pattern = [];
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}
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class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
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2016-04-13 16:02:26 +08:00
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class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
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class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, srem>;
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class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
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class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>;
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2015-08-18 22:40:43 +08:00
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2016-02-25 20:53:29 +08:00
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class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
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uimm5_inssize_plus1, MipsIns>;
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class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
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class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
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MipsIns>;
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2016-03-24 16:02:09 +08:00
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class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>;
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class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
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II_DMTC1, bitconvert>;
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class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>;
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2016-02-25 20:53:29 +08:00
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2016-03-31 16:51:24 +08:00
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class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>;
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class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
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II_DMFC1, bitconvert>;
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class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>;
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2016-04-08 15:27:26 +08:00
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class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>;
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class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
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II_DADDIU, immSExt16, add>,
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IsAsCheapAsAMove;
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class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
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2016-04-27 19:31:44 +08:00
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class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
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InstrItinClass Itin = NoItinerary,
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SDPatternOperator OpNode = null_frag>
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: MipsR6Inst {
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dag OutOperandList = (outs RO:$rd);
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dag InOperandList = (ins RO:$rs, RO:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
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list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
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InstrItinClass Itinerary = Itin;
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Format Form = FrmR;
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string BaseOpcode = instr_asm;
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let isCommutable = 0;
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let isReMaterializable = 1;
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let TwoOperandAliasConstraint = "$rd = $rs";
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}
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class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
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class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
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2016-04-21 22:32:12 +08:00
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class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
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2015-08-12 20:45:16 +08:00
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "MicroMipsR6" in {
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def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
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ISA_MICROMIPS64R6;
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2015-08-18 22:40:43 +08:00
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def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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2016-02-25 20:53:29 +08:00
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def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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2016-03-24 16:02:09 +08:00
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def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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2016-03-31 16:51:24 +08:00
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def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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2016-04-08 15:27:26 +08:00
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def DADD_MM64R6: StdMMR6Rel, DADD_MM64R6_DESC, DADD_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DADDIU_MM64R6: StdMMR6Rel, DADDIU_MM64R6_DESC, DADDIU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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2016-04-21 22:32:12 +08:00
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def LDPC_MM64R6 : R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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2016-04-27 19:31:44 +08:00
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def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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2015-08-12 20:45:16 +08:00
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}
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2016-03-24 16:02:09 +08:00
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//===----------------------------------------------------------------------===//
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2016-04-08 15:27:26 +08:00
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//
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// Arbitrary patterns that map to one or more instructions
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//
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//===----------------------------------------------------------------------===//
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def : MipsPat<(MipsLo tglobaladdr:$in),
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(DADDIU_MM64R6 ZERO_64, tglobaladdr:$in)>, ISA_MICROMIPS64R6;
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def : MipsPat<(MipsLo tblockaddress:$in),
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(DADDIU_MM64R6 ZERO_64, tblockaddress:$in)>, ISA_MICROMIPS64R6;
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def : MipsPat<(MipsLo tjumptable:$in),
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(DADDIU_MM64R6 ZERO_64, tjumptable:$in)>, ISA_MICROMIPS64R6;
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def : MipsPat<(MipsLo tconstpool:$in),
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(DADDIU_MM64R6 ZERO_64, tconstpool:$in)>, ISA_MICROMIPS64R6;
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def : MipsPat<(MipsLo tglobaltlsaddr:$in),
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(DADDIU_MM64R6 ZERO_64, tglobaltlsaddr:$in)>, ISA_MICROMIPS64R6;
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def : MipsPat<(MipsLo texternalsym:$in),
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(DADDIU_MM64R6 ZERO_64, texternalsym:$in)>, ISA_MICROMIPS64R6;
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def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
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(DADDIU_MM64R6 GPR64:$hi, tglobaladdr:$lo)>, ISA_MICROMIPS64R6;
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def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
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(DADDIU_MM64R6 GPR64:$hi, tblockaddress:$lo)>, ISA_MICROMIPS64R6;
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def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
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(DADDIU_MM64R6 GPR64:$hi, tjumptable:$lo)>, ISA_MICROMIPS64R6;
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def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
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(DADDIU_MM64R6 GPR64:$hi, tconstpool:$lo)>, ISA_MICROMIPS64R6;
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def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
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(DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6;
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def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
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(DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
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def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
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(DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
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def : WrapperPat<tglobaladdr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
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def : WrapperPat<tconstpool, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
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def : WrapperPat<texternalsym, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
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def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
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def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
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def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
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2016-04-27 19:31:44 +08:00
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// Carry pattern
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def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
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(DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
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2016-04-08 15:27:26 +08:00
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//===----------------------------------------------------------------------===//
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//
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2016-03-24 16:02:09 +08:00
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// Instruction aliases
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2016-04-08 15:27:26 +08:00
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//
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2016-03-24 16:02:09 +08:00
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//===----------------------------------------------------------------------===//
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2016-04-08 15:27:26 +08:00
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2016-03-24 16:02:09 +08:00
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def : MipsInstAlias<"dmtc0 $rt, $rd",
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(DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
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2016-03-31 16:51:24 +08:00
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def : MipsInstAlias<"dmfc0 $rt, $rd",
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(DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
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ISA_MICROMIPS64R6;
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2016-04-08 15:27:26 +08:00
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def : MipsInstAlias<"daddu $rs, $rt, $imm",
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(DADDIU_MM64R6 GPR64Opnd:$rs,
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GPR64Opnd:$rt,
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simm16_64:$imm),
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0>, ISA_MICROMIPS64R6;
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def : MipsInstAlias<"daddu $rs, $imm",
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(DADDIU_MM64R6 GPR64Opnd:$rs,
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GPR64Opnd:$rs,
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simm16_64:$imm),
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0>, ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dsubu $rt, $rs, $imm",
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(DADDIU_MM64R6 GPR64Opnd:$rt,
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GPR64Opnd:$rs,
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InvertedImOperand64:$imm),
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0>, ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dsubu $rs, $imm",
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(DADDIU_MM64R6 GPR64Opnd:$rs,
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GPR64Opnd:$rs,
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InvertedImOperand64:$imm),
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0>, ISA_MICROMIPS64R6;
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2016-04-27 19:31:44 +08:00
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def : MipsInstAlias<"dneg $rt, $rs",
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(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
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ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dneg $rt",
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(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
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ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dnegu $rt, $rs",
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(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
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ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dnegu $rt",
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(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
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ISA_MICROMIPS64R6;
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