2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CHECK --check-prefix CHECK-64
|
2018-02-28 05:31:11 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-target
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2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CHECK --check-prefix CHECK-64
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// RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CHECK --check-prefix CHECK-32
|
2018-02-28 05:31:11 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-target
|
2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CHECK --check-prefix CHECK-32
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2017-10-04 22:12:09 +08:00
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2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY0 %s
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2018-02-28 05:31:11 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-target
|
2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY0 %s
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// RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY0 %s
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2018-02-28 05:31:11 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-target
|
2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY0 %s
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2017-12-30 02:07:07 +08:00
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// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
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2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap %s --check-prefix LAMBDA --check-prefix LAMBDA-64
|
2018-02-28 05:31:11 +08:00
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// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-target
|
2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap %s --check-prefix LAMBDA --check-prefix LAMBDA-64
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2017-10-04 22:12:09 +08:00
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2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY1 %s
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2018-02-28 05:31:11 +08:00
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// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-target
|
2018-07-12 04:26:20 +08:00
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// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-target | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY1 %s
|
2017-12-30 02:07:07 +08:00
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// SIMD-ONLY1-NOT: {{__kmpc|__tgt}}
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2017-10-04 22:12:09 +08:00
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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struct St {
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int a, b;
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St() : a(0), b(0) {}
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St(const St &st) : a(st.a + st.b), b(0) {}
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~St() {}
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};
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volatile int g = 1212;
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|
volatile int &g1 = g;
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template <class T>
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struct S {
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T f;
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S(T a) : f(a + g) {}
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S() : f(g) {}
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S(const S &s, St t = St()) : f(s.f + t.a) {}
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|
operator T() { return T(); }
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|
~S() {}
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|
};
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// CHECK-DAG: [[S_FLOAT_TY:%.+]] = type { float }
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// CHECK-DAG: [[S_INT_TY:%.+]] = type { i{{[0-9]+}} }
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|
// CHECK-DAG: [[ST_TY:%.+]] = type { i{{[0-9]+}}, i{{[0-9]+}} }
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|
template <typename T>
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|
T tmain() {
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|
S<T> test;
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|
T t_var = T();
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|
T vec[] = {1, 2};
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|
S<T> s_arr[] = {1, 2};
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|
S<T> &var = test;
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|
#pragma omp target
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|
#pragma omp teams distribute firstprivate(t_var, vec, s_arr, var)
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|
for (int i = 0; i < 2; ++i) {
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|
vec[i] = t_var;
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|
s_arr[i] = var;
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|
}
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|
return T();
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|
}
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// CHECK-DAG: [[TEST:@.+]] = global [[S_FLOAT_TY]] zeroinitializer,
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|
S<float> test;
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|
// CHECK-DAG: [[T_VAR:@.+]] = global i{{[0-9]+}} 333,
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|
int t_var = 333;
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|
// CHECK-DAG: [[VEC:@.+]] = global [2 x i{{[0-9]+}}] [i{{[0-9]+}} 1, i{{[0-9]+}} 2],
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|
int vec[] = {1, 2};
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|
// CHECK-DAG: [[S_ARR:@.+]] = global [2 x [[S_FLOAT_TY]]] zeroinitializer,
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|
S<float> s_arr[] = {1, 2};
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|
// CHECK-DAG: [[VAR:@.+]] = global [[S_FLOAT_TY]] zeroinitializer,
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|
S<float> var(3);
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|
// CHECK-DAG: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0,
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|
|
int main() {
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|
static int sivar;
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|
#ifdef LAMBDA
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// LAMBDA: [[G:@.+]] = global i{{[0-9]+}} 1212,
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|
// LAMBDA-LABEL: @main
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|
// LAMBDA: call void [[OUTER_LAMBDA:@.+]](
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|
[&]() {
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|
// LAMBDA: define{{.*}} internal{{.*}} void [[OUTER_LAMBDA]](
|
2017-12-02 05:31:08 +08:00
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|
// LAMBDA: call i32 @__tgt_target_teams(i64 -1, i8* @{{[^,]+}}, i32 3, i8** %{{[^,]+}}, i8** %{{[^,]+}}, i{{64|32}}* {{.+}}@{{[^,]+}}, i32 0, i32 0), i64* {{.+}}@{{[^,]+}}, i32 0, i32 0), i32 0, i32 0)
|
2017-10-04 22:12:09 +08:00
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|
// LAMBDA: call void @[[LOFFL1:.+]](i{{64|32}} %{{.+}})
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|
// LAMBDA: ret
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|
|
#pragma omp target
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|
#pragma omp teams distribute firstprivate(g, g1, sivar)
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|
for (int i = 0; i < 2; ++i) {
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|
// LAMBDA: define{{.*}} internal{{.*}} void @[[LOFFL1]](i{{64|32}} {{%.+}}, i{{64|32}} {{%.+}})
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// LAMBDA: {{%.+}} = alloca i{{[0-9]+}},
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// LAMBDA: {{%.+}} = alloca i{{[0-9]+}},
|
2017-10-06 01:51:39 +08:00
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// LAMBDA: {{%.+}} = alloca i{{[0-9]+}},
|
2017-10-04 22:12:09 +08:00
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// LAMBDA: [[G_CAST:%.+]] = alloca i{{[0-9]+}},
|
2017-10-07 00:17:25 +08:00
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// LAMBDA: [[G1_CAST:%.+]] = alloca i{{[0-9]+}},
|
2017-10-04 22:12:09 +08:00
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// LAMBDA: [[SIVAR_CAST:%.+]] = alloca i{{[0-9]+}},
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// LAMBDA-DAG: [[G_CAST_VAL:%.+]] = load{{.+}} [[G_CAST]],
|
2017-10-07 00:17:25 +08:00
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// LAMBDA-DAG: [[G1_CAST_VAL:%.+]] = load{{.+}} [[G1_CAST]],
|
2017-10-04 22:12:09 +08:00
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|
// LAMBDA-DAG: [[SIVAR_CAST_VAL:%.+]] = load{{.+}} [[SIVAR_CAST]],
|
2017-10-07 00:17:25 +08:00
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|
// LAMBDA: call void {{.+}} @__kmpc_fork_teams({{.+}}, i32 3, {{.+}} @[[LOUTL1:.+]] to {{.+}}, {{.+}} [[G_CAST_VAL]], {{.+}} [[G1_CAST_VAL]], {{.+}} [[SIVAR_CAST_VAL]])
|
2017-10-04 22:12:09 +08:00
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|
// LAMBDA: ret void
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|
// LAMBDA: define internal void @[[LOUTL1]]({{.+}})
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|
// Skip global and bound tid vars
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|
|
// LAMBDA: {{.+}} = alloca i32*,
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// LAMBDA: {{.+}} = alloca i32*,
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// LAMBDA: [[G_ADDR:%.+]] = alloca i{{[0-9]+}},
|
2017-10-07 00:17:25 +08:00
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// LAMBDA: [[G1_ADDR:%.+]] = alloca i{{[0-9]+}},
|
2017-10-04 22:12:09 +08:00
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// LAMBDA: [[SIVAR_ADDR:%.+]] = alloca i{{[0-9]+}},
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|
// LAMBDA: [[G1_TMP:%.+]] = alloca i32*,
|
2017-10-07 00:17:25 +08:00
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|
// skip loop vars
|
2017-10-04 22:12:09 +08:00
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|
// LAMBDA-DAG: store {{.+}}, {{.+}} [[G_ADDR]],
|
2017-10-07 00:17:25 +08:00
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|
// LAMBDA-DAG: store {{.+}}, {{.+}} [[G1_ADDR]],
|
2017-10-04 22:12:09 +08:00
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|
// LAMBDA-DAG: store {{.+}}, {{.+}} [[SIVAR_ADDR]],
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|
// LAMBDA-DAG: [[G_CONV:%.+]] = bitcast {{.+}} [[G_ADDR]] to
|
2017-10-07 00:17:25 +08:00
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|
// LAMBDA-DAG: [[G1_CONV:%.+]] = bitcast {{.+}} [[G1_ADDR]] to
|
2017-10-04 22:12:09 +08:00
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|
|
// LAMBDA-DAG: [[SIVAR_CONV:%.+]] = bitcast {{.+}} [[SIVAR_ADDR]] to
|
2017-10-07 00:17:25 +08:00
|
|
|
// LAMBDA-DAG: store{{.+}} [[G1_CONV]], {{.+}} [[G1_TMP]],
|
2017-10-04 22:12:09 +08:00
|
|
|
g = 1;
|
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|
|
g1 = 1;
|
|
|
|
sivar = 2;
|
|
|
|
// LAMBDA: call void @__kmpc_for_static_init_4(
|
|
|
|
// LAMBDA-DAG: store{{.+}} 1, {{.+}} [[G_CONV]],
|
2017-10-07 00:17:25 +08:00
|
|
|
// LAMBDA-DAG: [[G1:%.+]] = load{{.+}}, {{.+}}* [[G1_TMP]]
|
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|
|
// LAMBDA-DAG: store{{.+}} 1, {{.+}} [[G1]],
|
2017-10-04 22:12:09 +08:00
|
|
|
// LAMBDA-DAG: store{{.+}} 2, {{.+}} [[SIVAR_CONV]],
|
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|
|
// LAMBDA-DAG: [[G1_REF:%.+]] = load{{.+}}, {{.+}} [[G1_TMP]],
|
|
|
|
// LAMBDA-DAG: store{{.+}} 1, {{.+}} [[G1_REF]],
|
|
|
|
// LAMBDA: call void [[INNER_LAMBDA:@.+]](
|
|
|
|
// LAMBDA: call void @__kmpc_for_static_fini(
|
|
|
|
[&]() {
|
|
|
|
// LAMBDA: define {{.+}} void [[INNER_LAMBDA]](%{{.+}}* [[ARG_PTR:%.+]])
|
|
|
|
// LAMBDA: store %{{.+}}* [[ARG_PTR]], %{{.+}}** [[ARG_PTR_REF:%.+]],
|
|
|
|
g = 2;
|
|
|
|
g1 = 2;
|
|
|
|
sivar = 4;
|
|
|
|
// LAMBDA: [[ARG_PTR:%.+]] = load %{{.+}}*, %{{.+}}** [[ARG_PTR_REF]]
|
|
|
|
|
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|
|
// LAMBDA: [[G_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
|
|
|
|
// LAMBDA: [[G_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[G_PTR_REF]]
|
|
|
|
// LAMBDA: store i{{[0-9]+}} 2, i{{[0-9]+}}* [[G_REF]]
|
2017-10-07 00:17:25 +08:00
|
|
|
// LAMBDA: [[G1_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
|
|
|
|
// LAMBDA: [[G1_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[G1_PTR_REF]]
|
|
|
|
// LAMBDA: store i{{[0-9]+}} 2, i{{[0-9]+}}* [[G1_REF]]
|
|
|
|
// LAMBDA: [[SIVAR_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
|
2017-10-04 22:12:09 +08:00
|
|
|
// LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]]
|
|
|
|
// LAMBDA: store i{{[0-9]+}} 4, i{{[0-9]+}}* [[SIVAR_REF]]
|
|
|
|
}();
|
|
|
|
}
|
|
|
|
}();
|
|
|
|
return 0;
|
|
|
|
#else
|
|
|
|
#pragma omp target
|
|
|
|
#pragma omp teams distribute firstprivate(t_var, vec, s_arr, var, sivar)
|
|
|
|
for (int i = 0; i < 2; ++i) {
|
|
|
|
vec[i] = t_var;
|
|
|
|
s_arr[i] = var;
|
|
|
|
sivar += i;
|
|
|
|
}
|
|
|
|
return tmain<int>();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
// CHECK: define {{.*}}i{{[0-9]+}} @main()
|
2017-12-02 05:31:08 +08:00
|
|
|
// CHECK: call i32 @__tgt_target_teams(i64 -1, i8* @{{[^,]+}}, i32 5, i8** %{{[^,]+}}, i8** %{{[^,]+}}, i{{64|32}}* {{.+}}@{{[^,]+}}, i32 0, i32 0), i64* {{.+}}@{{[^,]+}}, i32 0, i32 0), i32 0, i32 0)
|
2017-10-04 22:12:09 +08:00
|
|
|
// CHECK: call void @[[OFFL1:.+]](i{{64|32}} %{{.+}})
|
|
|
|
// CHECK: {{%.+}} = call{{.*}} i32 @[[TMAIN_INT:.+]]()
|
|
|
|
// CHECK: ret
|
|
|
|
|
|
|
|
// CHECK: define{{.*}} void @[[OFFL1]]({{.+}})
|
|
|
|
// CHECK: [[T_VAR_PRIV:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[VEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}]*,
|
|
|
|
// CHECK: [[S_ARR_PRIV:%.+]] = alloca [2 x [[S_FLOAT_TY]]]*,
|
|
|
|
// CHECK: [[VAR_PRIV:%.+]] = alloca [[S_FLOAT_TY]]*,
|
|
|
|
// CHECK: [[SIVAR_PRIV:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[T_VAR_CAST:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[SIVAR_CAST:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
|
|
|
|
// CHECK-DAG: [[VEC_TE_PAR:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_PRIV]],
|
|
|
|
// CHECK-DAG: [[T_VAR_TE_PAR:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[T_VAR_CAST]],
|
|
|
|
// CHECK-DAG: [[S_ARR_TE_PAR:%.+]] = load [2 x [[S_FLOAT_TY]]]*, [2 x [[S_FLOAT_TY]]]** [[S_ARR_PRIV]],
|
|
|
|
// CHECK-DAG: [[VAR_TE_PAR:%.+]] = load [[S_FLOAT_TY]]*, [[S_FLOAT_TY]]** [[VAR_PRIV]],
|
|
|
|
// CHECK-DAG: [[SIVAR_TE_PAR:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[SIVAR_CAST]],
|
|
|
|
|
|
|
|
// CHECK: call void {{.+}} @__kmpc_fork_teams({{.+}}, i32 5, {{.+}} @[[OUTL1:.+]] to {{.+}}, [2 x i{{[0-9]+}}]* [[VEC_TE_PAR]], i{{[0-9]+}} [[T_VAR_TE_PAR]], [2 x [[S_FLOAT_TY]]]* [[S_ARR_TE_PAR]], [[S_FLOAT_TY]]* [[VAR_TE_PAR]], i{{[0-9]+}} [[SIVAR_TE_PAR]])
|
|
|
|
// CHECK: ret void
|
|
|
|
|
|
|
|
// CHECK: define internal void @[[OUTL1]]({{.+}})
|
|
|
|
// Skip global and bound tid vars
|
|
|
|
// CHECK: {{.+}} = alloca i32*,
|
|
|
|
// CHECK: {{.+}} = alloca i32*,
|
|
|
|
// CHECK: [[VEC_ADDR:%.+]] = alloca [2 x i{{[0-9]+}}]*,
|
|
|
|
// CHECK: [[T_VAR_ADDR:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[S_ARR_ADDR:%.+]] = alloca [2 x [[S_FLOAT_TY]]]*,
|
|
|
|
// CHECK: [[VAR_ADDR:%.+]] = alloca [[S_FLOAT_TY]]*,
|
|
|
|
// CHECK: [[SIVAR_ADDR:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
// Skip temp vars for loop
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[VEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}],
|
|
|
|
// CHECK: [[S_ARR_PRIV:%.+]] = alloca [2 x [[S_FLOAT_TY]]],
|
|
|
|
// CHECK: [[AGG_TMP1:%.+]] = alloca [[ST_TY]],
|
|
|
|
// CHECK: [[VAR_PRIV:%.+]] = alloca [[S_FLOAT_TY]],
|
|
|
|
// CHECK: [[AGG_TMP2:%.+]] = alloca [[ST_TY]],
|
|
|
|
|
|
|
|
// param copy
|
|
|
|
// CHECK: store [2 x i{{[0-9]+}}]* {{.+}}, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
|
|
|
|
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[T_VAR_ADDR]],
|
|
|
|
// CHECK: store [2 x [[S_FLOAT_TY]]]* {{.+}}, [2 x [[S_FLOAT_TY]]]** [[S_ARR_ADDR]],
|
|
|
|
// CHECK: store [[S_FLOAT_TY]]* {{.+}}, [[S_FLOAT_TY]]** [[VAR_ADDR]],
|
|
|
|
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
|
|
|
|
|
|
|
|
// T_VAR and SIVAR
|
2018-05-04 01:22:04 +08:00
|
|
|
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
|
|
|
|
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
|
2017-10-04 22:12:09 +08:00
|
|
|
|
|
|
|
// preparation vars
|
|
|
|
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
|
|
|
|
// CHECK-DAG: [[S_ARR_ADDR_REF:%.+]] = load [2 x [[S_FLOAT_TY]]]*, [2 x [[S_FLOAT_TY]]]** [[S_ARR_ADDR]],
|
|
|
|
// CHECK-DAG: [[VAR_ADDR_REF:%.+]] = load{{.+}} [[VAR_ADDR]],
|
|
|
|
|
|
|
|
// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
|
|
|
|
// CHECK-DAG: [[VEC_DEST_PRIV:%.+]] = bitcast [2 x i{{[0-9]+}}]* [[VEC_PRIV]] to i8*
|
|
|
|
// CHECK-DAG: [[VEC_SRC:%.+]] = bitcast [2 x i{{[0-9]+}}]* [[VEC_ADDR_VAL]] to i8*
|
Change memcpy/memove/memset to have dest and source alignment attributes (Step 1).
Summary:
Upstream LLVM is changing the the prototypes of the @llvm.memcpy/memmove/memset
intrinsics. This change updates the Clang tests for this change.
The @llvm.memcpy/memmove/memset intrinsics currently have an explicit argument
which is required to be a constant integer. It represents the alignment of the
dest (and source), and so must be the minimum of the actual alignment of the
two.
This change removes the alignment argument in favour of placing the alignment
attribute on the source and destination pointers of the memory intrinsic call.
For example, code which used to read:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 100, i32 4, i1 false)
will now read
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 100, i1 false)
At this time the source and destination alignments must be the same (Step 1).
Step 2 of the change, to be landed shortly, will relax that contraint and allow
the source and destination to have different alignments.
llvm-svn: 322964
2018-01-20 01:12:54 +08:00
|
|
|
// CHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[VEC_DEST_PRIV]], i8* align {{[0-9]+}} [[VEC_SRC]], {{.+}})
|
2017-10-04 22:12:09 +08:00
|
|
|
|
|
|
|
// firstprivate(s_arr)
|
|
|
|
// CHECK-DAG: [[S_ARR_PRIV_BGN:%.+]] = getelementptr{{.*}} [2 x [[S_FLOAT_TY]]], [2 x [[S_FLOAT_TY]]]* [[S_ARR_PRIV]],
|
|
|
|
// CHECK-DAG: [[S_ARR_ADDR_BGN:%.+]] = bitcast [2 x [[S_FLOAT_TY]]]* [[S_ARR_ADDR_REF]] to
|
|
|
|
// CHECK-DAG: [[S_ARR_FIN:%.+]] = icmp{{.+}} [[S_ARR_PRIV_BGN]],
|
|
|
|
// CHECK-DAG: [[S_ARR_SRC_COPY:%.+]] = phi{{.+}} [ [[S_ARR_ADDR_BGN]], {{.+}} ], [ [[S_ARR_SRC:%.+]], {{.+}} ]
|
|
|
|
// CHECK-DAG: [[S_ARR_DST_COPY:%.+]] = phi{{.+}} [ [[S_ARR_PRIV_BGN]], {{.+}}], [ [[S_ARR_DST:%.+]], {{.+}} ]
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP1]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[S_ARR_DST_COPY]], {{.+}} [[S_ARR_SRC_COPY]], {{.+}} [[AGG_TMP1]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP1]])
|
|
|
|
// CHECK-DAG: [[S_ARR_DST]] = getelementptr {{.+}} [[S_ARR_DST_COPY]],
|
|
|
|
// CHECK-DAG: [[S_ARR_SRC]] = getelementptr {{.+}} [[S_ARR_SRC_COPY]],
|
|
|
|
|
|
|
|
// firstprivate(var)
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[VAR_PRIV]], {{.+}} [[VAR_ADDR_REF]], {{.+}} [[AGG_TMP2]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
|
|
|
|
|
|
|
|
// CHECK: call void @__kmpc_for_static_init_4(
|
2018-05-04 01:22:04 +08:00
|
|
|
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
|
|
|
|
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
|
2017-10-04 22:12:09 +08:00
|
|
|
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
|
|
|
|
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
|
|
|
|
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
|
2018-05-04 01:22:04 +08:00
|
|
|
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
|
|
|
|
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
|
2017-10-04 22:12:09 +08:00
|
|
|
// CHECK: call void @__kmpc_for_static_fini(
|
|
|
|
// CHECK: ret void
|
|
|
|
|
|
|
|
// CHECK: define{{.*}} i{{[0-9]+}} @[[TMAIN_INT]]()
|
2017-12-02 05:31:08 +08:00
|
|
|
// CHECK: call i32 @__tgt_target_teams(i64 -1, i8* @{{[^,]+}}, i32 4, i8** %{{[^,]+}}, i8** %{{[^,]+}}, i{{64|32}}* {{.+}}@{{[^,]+}}, i32 0, i32 0), i64* {{.+}}@{{[^,]+}}, i32 0, i32 0), i32 0, i32 0)
|
2017-10-04 22:12:09 +08:00
|
|
|
// CHECK: call void @[[TOFFL1:.+]](i{{64|32}} %{{.+}})
|
|
|
|
// CHECK: ret
|
|
|
|
|
|
|
|
// CHECK: define {{.*}}void @[[TOFFL1]]({{.+}})
|
|
|
|
// CHECK: [[TT_VAR_PRIV:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[TVEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}]*,
|
|
|
|
// CHECK: [[TS_ARR_PRIV:%.+]] = alloca [2 x [[S_INT_TY]]]*,
|
|
|
|
// CHECK: [[TVAR_PRIV:%.+]] = alloca [[S_INT_TY]]*,
|
|
|
|
// CHECK: [[TT_VAR_CAST:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
|
|
|
|
// CHECK-DAG: [[TVEC_TE_PAR:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[TVEC_PRIV]],
|
|
|
|
// CHECK-DAG: [[TT_VAR_TE_PAR:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[TT_VAR_CAST]],
|
|
|
|
// CHECK-DAG: [[TS_ARR_TE_PAR:%.+]] = load [2 x [[S_INT_TY]]]*, [2 x [[S_INT_TY]]]** [[TS_ARR_PRIV]],
|
|
|
|
// CHECK-DAG: [[TVAR_TE_PAR:%.+]] = load [[S_INT_TY]]*, [[S_INT_TY]]** [[TVAR_PRIV]],
|
|
|
|
|
2019-05-24 02:19:54 +08:00
|
|
|
// CHECK: [[TVAR_TE_PAR:%.+]] = load [[S_INT_TY]]*, [[S_INT_TY]]** %
|
2017-10-04 22:12:09 +08:00
|
|
|
// CHECK: call void {{.+}} @__kmpc_fork_teams({{.+}}, i32 4, {{.+}} @[[TOUTL1:.+]] to {{.+}}, [2 x i{{[0-9]+}}]* [[TVEC_TE_PAR]], i{{[0-9]+}} [[TT_VAR_TE_PAR]], [2 x [[S_INT_TY]]]* [[TS_ARR_TE_PAR]], [[S_INT_TY]]* [[TVAR_TE_PAR]])
|
|
|
|
// CHECK: ret void
|
|
|
|
|
|
|
|
// CHECK: define internal void @[[TOUTL1]]({{.+}})
|
|
|
|
// Skip global and bound tid vars
|
|
|
|
// CHECK: {{.+}} = alloca i32*,
|
|
|
|
// CHECK: {{.+}} = alloca i32*,
|
|
|
|
// CHECK: [[VEC_ADDR:%.+]] = alloca [2 x i{{[0-9]+}}]*,
|
|
|
|
// CHECK: [[T_VAR_ADDR:%.+]] = alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[S_ARR_ADDR:%.+]] = alloca [2 x [[S_INT_TY]]]*,
|
|
|
|
// CHECK: [[VAR_ADDR:%.+]] = alloca [[S_INT_TY]]*,
|
2019-05-24 02:19:54 +08:00
|
|
|
// CHECK: [[TMP_VAR_ADDR:%.+]] = alloca [[S_INT_TY]]*,
|
2017-10-04 22:12:09 +08:00
|
|
|
// Skip temp vars for loop
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: alloca i{{[0-9]+}},
|
|
|
|
// CHECK: [[VEC_PRIV:%.+]] = alloca [2 x i{{[0-9]+}}],
|
|
|
|
// CHECK: [[S_ARR_PRIV:%.+]] = alloca [2 x [[S_INT_TY]]],
|
|
|
|
// CHECK: [[AGG_TMP1:%.+]] = alloca [[ST_TY]],
|
|
|
|
// CHECK: [[VAR_PRIV:%.+]] = alloca [[S_INT_TY]],
|
|
|
|
// CHECK: [[AGG_TMP2:%.+]] = alloca [[ST_TY]],
|
|
|
|
// CHECK: [[TMP:%.+]] = alloca [[S_INT_TY]]*,
|
|
|
|
|
|
|
|
// param copy
|
|
|
|
// CHECK: store [2 x i{{[0-9]+}}]* {{.+}}, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
|
|
|
|
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[T_VAR_ADDR]],
|
|
|
|
// CHECK: store [2 x [[S_INT_TY]]]* {{.+}}, [2 x [[S_INT_TY]]]** [[S_ARR_ADDR]],
|
|
|
|
// CHECK: store [[S_INT_TY]]* {{.+}}, [[S_INT_TY]]** [[VAR_ADDR]],
|
|
|
|
|
|
|
|
|
|
|
|
// T_VAR and preparation variables
|
|
|
|
// CHECK: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
|
|
|
|
// CHECK-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
|
|
|
|
// CHECK: [[S_ARR_ADDR_REF:%.+]] = load [2 x [[S_INT_TY]]]*, [2 x [[S_INT_TY]]]** [[S_ARR_ADDR]],
|
|
|
|
|
|
|
|
// firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
|
2019-05-24 02:19:54 +08:00
|
|
|
// CHECK-DAG: [[VEC_DEST_PRIV:%.+]] = bitcast [2 x i{{[0-9]+}}]* [[VEC_PRIV]] to i8*
|
|
|
|
// CHECK-DAG: [[VEC_SRC:%.+]] = bitcast [2 x i{{[0-9]+}}]* [[VEC_ADDR_VAL]] to i8*
|
Change memcpy/memove/memset to have dest and source alignment attributes (Step 1).
Summary:
Upstream LLVM is changing the the prototypes of the @llvm.memcpy/memmove/memset
intrinsics. This change updates the Clang tests for this change.
The @llvm.memcpy/memmove/memset intrinsics currently have an explicit argument
which is required to be a constant integer. It represents the alignment of the
dest (and source), and so must be the minimum of the actual alignment of the
two.
This change removes the alignment argument in favour of placing the alignment
attribute on the source and destination pointers of the memory intrinsic call.
For example, code which used to read:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 100, i32 4, i1 false)
will now read
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 100, i1 false)
At this time the source and destination alignments must be the same (Step 1).
Step 2 of the change, to be landed shortly, will relax that contraint and allow
the source and destination to have different alignments.
llvm-svn: 322964
2018-01-20 01:12:54 +08:00
|
|
|
// CHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[VEC_DEST_PRIV]], i8* align {{[0-9]+}} [[VEC_SRC]], {{.+}})
|
2017-10-04 22:12:09 +08:00
|
|
|
|
|
|
|
// firstprivate(s_arr)
|
|
|
|
// CHECK-DAG: [[S_ARR_PRIV_BGN:%.+]] = getelementptr{{.*}} [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* [[S_ARR_PRIV]],
|
|
|
|
// CHECK-DAG: [[S_ARR_ADDR_BGN:%.+]] = bitcast [2 x [[S_INT_TY]]]* [[S_ARR_ADDR_REF]] to
|
|
|
|
// CHECK-DAG: [[S_ARR_FIN:%.+]] = icmp{{.+}} [[S_ARR_PRIV_BGN]],
|
|
|
|
// CHECK-DAG: [[S_ARR_SRC_COPY:%.+]] = phi{{.+}} [ [[S_ARR_ADDR_BGN]], {{.+}} ], [ [[S_ARR_SRC:%.+]], {{.+}} ]
|
|
|
|
// CHECK-DAG: [[S_ARR_DST_COPY:%.+]] = phi{{.+}} [ [[S_ARR_PRIV_BGN]], {{.+}} ], [ [[S_ARR_DST:%.+]], {{.+}} ]
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP1]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[S_ARR_DST_COPY]], {{.+}} [[S_ARR_SRC_COPY]], {{.+}} [[AGG_TMP1]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP1]])
|
|
|
|
// CHECK-DAG: [[S_ARR_DST]] = getelementptr {{.+}} [[S_ARR_DST_COPY]],
|
|
|
|
// CHECK-DAG: [[S_ARR_SRC]] = getelementptr {{.+}} [[S_ARR_SRC_COPY]],
|
|
|
|
|
|
|
|
// firstprivate(var)
|
2019-05-24 02:19:54 +08:00
|
|
|
// CHECK-DAG: [[VAR_ADDR_REF:%.+]] = load{{.+}} [[TMP_VAR_ADDR]],
|
2017-10-04 22:12:09 +08:00
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[VAR_PRIV]], {{.+}} [[VAR_ADDR_REF]], {{.+}} [[AGG_TMP2]])
|
|
|
|
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
|
|
|
|
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
|
|
|
|
|
|
|
|
// CHECK: call void @__kmpc_for_static_init_4(
|
2018-05-04 01:22:04 +08:00
|
|
|
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
|
|
|
|
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
|
2017-10-04 22:12:09 +08:00
|
|
|
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
|
|
|
|
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
|
|
|
|
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
|
|
|
|
// CHECK: call void @__kmpc_for_static_fini(
|
|
|
|
// CHECK: ret void
|
|
|
|
|
|
|
|
#endif
|