2012-12-12 05:25:42 +08:00
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//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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2014-07-21 22:01:08 +08:00
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#include "MCTargetDesc/AMDGPUFixupKinds.h"
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2012-12-12 05:25:42 +08:00
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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2016-08-27 08:21:22 +08:00
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#include "llvm/MC/MCContext.h"
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2014-07-21 22:01:08 +08:00
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#include "llvm/MC/MCFixupKindInfo.h"
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2012-12-12 05:25:42 +08:00
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace {
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class AMDGPUAsmBackend : public MCAsmBackend {
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public:
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AMDGPUAsmBackend(const Target &T)
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: MCAsmBackend() {}
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2014-07-21 22:01:14 +08:00
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unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
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2016-08-27 08:21:22 +08:00
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void processFixupValue(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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const MCValue &Target, uint64_t &Value,
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bool &IsResolved) override;
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2014-04-29 15:57:24 +08:00
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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2017-04-05 18:16:14 +08:00
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uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;
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2014-04-29 15:57:24 +08:00
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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2012-12-12 05:25:42 +08:00
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return false;
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}
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2016-07-11 22:23:53 +08:00
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void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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MCInst &Res) const override {
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2016-12-23 09:38:06 +08:00
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llvm_unreachable("Not implemented");
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2012-12-12 05:25:42 +08:00
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}
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2014-04-29 15:57:24 +08:00
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bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
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2014-10-04 03:02:02 +08:00
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
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2014-07-21 22:01:08 +08:00
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
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2012-12-12 05:25:42 +08:00
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};
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} //End anonymous namespace
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2015-07-31 01:03:08 +08:00
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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2016-08-27 08:21:22 +08:00
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case AMDGPU::fixup_si_sopp_br:
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return 2;
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2016-05-14 04:39:26 +08:00
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case FK_SecRel_1:
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2015-07-31 01:03:08 +08:00
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case FK_Data_1:
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return 1;
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2016-05-14 04:39:26 +08:00
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case FK_SecRel_2:
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2015-07-31 01:03:08 +08:00
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case FK_Data_2:
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return 2;
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2016-05-14 04:39:26 +08:00
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case FK_SecRel_4:
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2015-07-31 01:03:08 +08:00
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case FK_Data_4:
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2016-06-15 04:29:59 +08:00
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case FK_PCRel_4:
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2015-07-31 01:03:08 +08:00
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return 4;
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2016-05-14 04:39:26 +08:00
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case FK_SecRel_8:
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2015-07-31 01:03:08 +08:00
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case FK_Data_8:
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return 8;
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default:
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llvm_unreachable("Unknown fixup kind!");
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}
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}
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2016-08-27 08:21:22 +08:00
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext *Ctx) {
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int64_t SignedValue = static_cast<int64_t>(Value);
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switch (Fixup.getKind()) {
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case AMDGPU::fixup_si_sopp_br: {
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int64_t BrImm = (SignedValue - 4) / 4;
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if (Ctx && !isInt<16>(BrImm))
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Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
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return BrImm;
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}
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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case FK_PCRel_4:
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2016-08-30 03:01:48 +08:00
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case FK_SecRel_4:
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2016-08-27 08:21:22 +08:00
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return Value;
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default:
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llvm_unreachable("unhandled fixup kind");
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}
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}
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void AMDGPUAsmBackend::processFixupValue(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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const MCValue &Target, uint64_t &Value,
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bool &IsResolved) {
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2016-10-08 00:01:18 +08:00
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MCValue Res;
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// When we have complex expressions like: BB0_1 + (BB0_2 - 4), which are
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// used for long branches, this function will be called with
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// IsResolved = false and Value set to some pre-computed value. In
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// the example above, the value would be:
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// (BB0_1 + (BB0_2 - 4)) - CurrentOffsetFromStartOfFunction.
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// This is not what we want. We just want the expression computation
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// only. The reason the MC layer subtracts the current offset from the
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// expression is because the fixup is of kind FK_PCRel_4.
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// For these scenarios, evaluateAsValue gives us the computation that we
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// want.
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if (!IsResolved && Fixup.getValue()->evaluateAsValue(Res, Layout) &&
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Res.isAbsolute()) {
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Value = Res.getConstant();
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IsResolved = true;
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}
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2016-08-27 08:21:22 +08:00
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if (IsResolved)
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[AMDGPU] Fix s_branch with -1 offset
Summary:
In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0.
'''
label:
s_branch label // should emit [0xff,0xff,0x82,0xbf]
'''
Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result.
Reviewers: vpykhtin, artem.tamazov, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl
Differential Revision: https://reviews.llvm.org/D24671
llvm-svn: 281896
2016-09-19 18:20:55 +08:00
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Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
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2016-08-27 08:21:22 +08:00
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}
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2012-12-17 23:14:54 +08:00
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void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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2014-03-29 14:26:49 +08:00
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unsigned DataSize, uint64_t Value,
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2017-04-05 18:16:14 +08:00
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bool IsPCRel, MCContext &Ctx) const {
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2016-08-27 08:21:22 +08:00
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if (!Value)
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return; // Doesn't change encoding.
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2012-12-17 23:14:54 +08:00
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2016-08-27 08:21:22 +08:00
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MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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[AMDGPU] Fix s_branch with -1 offset
Summary:
In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0.
'''
label:
s_branch label // should emit [0xff,0xff,0x82,0xbf]
'''
Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result.
Reviewers: vpykhtin, artem.tamazov, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl
Differential Revision: https://reviews.llvm.org/D24671
llvm-svn: 281896
2016-09-19 18:20:55 +08:00
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unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
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2016-08-27 08:21:22 +08:00
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uint32_t Offset = Fixup.getOffset();
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assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the bits from
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// the fixup value.
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for (unsigned i = 0; i != NumBytes; ++i)
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Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
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2012-12-17 23:14:54 +08:00
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}
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2013-04-16 01:51:21 +08:00
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2014-07-21 22:01:08 +08:00
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const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
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MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
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// name offset bits flags
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2014-07-21 22:01:14 +08:00
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{ "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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2014-07-21 22:01:08 +08:00
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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return Infos[Kind - FirstTargetFixupKind];
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}
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2014-10-04 03:02:02 +08:00
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bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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2015-04-17 19:12:43 +08:00
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OW->WriteZeros(Count);
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2014-10-04 03:02:02 +08:00
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return true;
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}
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2013-04-16 01:51:21 +08:00
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//===----------------------------------------------------------------------===//
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// ELFAMDGPUAsmBackend class
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//===----------------------------------------------------------------------===//
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2013-05-23 23:43:05 +08:00
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namespace {
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2013-04-16 01:51:21 +08:00
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class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
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2016-06-14 23:16:35 +08:00
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bool Is64Bit;
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2016-06-15 04:29:59 +08:00
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bool HasRelocationAddend;
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2015-06-23 05:03:54 +08:00
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2013-04-16 01:51:21 +08:00
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public:
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2016-06-15 04:29:59 +08:00
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ELFAMDGPUAsmBackend(const Target &T, const Triple &TT) :
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AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
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HasRelocationAddend(TT.getOS() == Triple::AMDHSA) { }
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2013-04-16 01:51:21 +08:00
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2015-04-15 06:14:34 +08:00
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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2016-06-15 04:29:59 +08:00
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return createAMDGPUELFObjectWriter(Is64Bit, HasRelocationAddend, OS);
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2013-04-16 01:51:21 +08:00
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}
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};
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2013-05-23 23:43:05 +08:00
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} // end anonymous namespace
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2013-09-09 10:37:14 +08:00
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MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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2016-07-26 01:18:28 +08:00
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const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options) {
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2015-06-23 05:03:54 +08:00
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// Use 64-bit ELF for amdgcn
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2016-06-15 04:29:59 +08:00
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return new ELFAMDGPUAsmBackend(T, TT);
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2013-04-16 01:51:21 +08:00
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}
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