2012-01-12 06:28:30 +08:00
|
|
|
//===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
|
2010-10-23 07:09:15 +08:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file defines the RABasic function pass, which provides a minimal
|
|
|
|
// implementation of the basic register allocator.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2012-06-21 06:52:24 +08:00
|
|
|
#include "AllocationOrder.h"
|
2011-04-06 05:40:37 +08:00
|
|
|
#include "LiveDebugVariables.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "RegAllocBase.h"
|
2010-10-23 07:09:15 +08:00
|
|
|
#include "Spiller.h"
|
2010-11-12 01:46:29 +08:00
|
|
|
#include "llvm/Analysis/AliasAnalysis.h"
|
2010-10-23 07:09:15 +08:00
|
|
|
#include "llvm/CodeGen/CalcSpillWeights.h"
|
2017-12-13 10:51:04 +08:00
|
|
|
#include "llvm/CodeGen/LiveIntervals.h"
|
2012-04-03 06:44:18 +08:00
|
|
|
#include "llvm/CodeGen/LiveRangeEdit.h"
|
2012-11-29 03:13:06 +08:00
|
|
|
#include "llvm/CodeGen/LiveRegMatrix.h"
|
2017-12-19 07:19:44 +08:00
|
|
|
#include "llvm/CodeGen/LiveStacks.h"
|
2013-06-18 03:00:36 +08:00
|
|
|
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
|
2010-10-23 07:09:15 +08:00
|
|
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
|
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
|
|
|
#include "llvm/CodeGen/MachineLoopInfo.h"
|
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2017-06-06 19:49:48 +08:00
|
|
|
#include "llvm/CodeGen/Passes.h"
|
2010-10-23 07:09:15 +08:00
|
|
|
#include "llvm/CodeGen/RegAllocRegistry.h"
|
2017-11-17 09:07:10 +08:00
|
|
|
#include "llvm/CodeGen/TargetRegisterInfo.h"
|
2012-11-29 03:13:06 +08:00
|
|
|
#include "llvm/CodeGen/VirtRegMap.h"
|
2012-12-04 00:50:05 +08:00
|
|
|
#include "llvm/PassAnalysisSupport.h"
|
|
|
|
#include "llvm/Support/Debug.h"
|
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2010-12-08 07:18:47 +08:00
|
|
|
#include <cstdlib>
|
2011-02-23 07:01:52 +08:00
|
|
|
#include <queue>
|
2010-10-27 02:34:01 +08:00
|
|
|
|
2010-10-23 07:09:15 +08:00
|
|
|
using namespace llvm;
|
|
|
|
|
2014-04-22 10:02:50 +08:00
|
|
|
#define DEBUG_TYPE "regalloc"
|
|
|
|
|
2010-10-23 07:09:15 +08:00
|
|
|
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
|
|
|
|
createBasicRegisterAllocator);
|
|
|
|
|
2011-02-23 07:01:52 +08:00
|
|
|
namespace {
|
|
|
|
struct CompSpillWeight {
|
|
|
|
bool operator()(LiveInterval *A, LiveInterval *B) const {
|
|
|
|
return A->weight < B->weight;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2010-11-26 00:42:51 +08:00
|
|
|
namespace {
|
2010-10-23 07:09:15 +08:00
|
|
|
/// RABasic provides a minimal implementation of the basic register allocation
|
|
|
|
/// algorithm. It prioritizes live virtual registers by spill weight and spills
|
|
|
|
/// whenever a register is unavailable. This is not practical in production but
|
|
|
|
/// provides a useful baseline both for measuring other allocators and comparing
|
|
|
|
/// the speed of the basic algorithm against other styles of allocators.
|
2017-06-03 06:46:31 +08:00
|
|
|
class RABasic : public MachineFunctionPass,
|
|
|
|
public RegAllocBase,
|
|
|
|
private LiveRangeEdit::Delegate {
|
2010-10-23 07:09:15 +08:00
|
|
|
// context
|
2010-12-01 07:18:47 +08:00
|
|
|
MachineFunction *MF;
|
2010-10-23 07:09:15 +08:00
|
|
|
|
|
|
|
// state
|
2014-03-06 13:51:42 +08:00
|
|
|
std::unique_ptr<Spiller> SpillerInstance;
|
2011-02-23 07:01:52 +08:00
|
|
|
std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
|
|
|
|
CompSpillWeight> Queue;
|
2012-02-09 02:54:35 +08:00
|
|
|
|
|
|
|
// Scratch space. Allocated here to avoid repeated malloc calls in
|
|
|
|
// selectOrSplit().
|
|
|
|
BitVector UsableRegs;
|
|
|
|
|
2017-06-03 06:46:31 +08:00
|
|
|
bool LRE_CanEraseVirtReg(unsigned) override;
|
|
|
|
void LRE_WillShrinkVirtReg(unsigned) override;
|
|
|
|
|
2010-10-23 07:09:15 +08:00
|
|
|
public:
|
|
|
|
RABasic();
|
|
|
|
|
|
|
|
/// Return the pass name.
|
2016-10-01 10:56:57 +08:00
|
|
|
StringRef getPassName() const override { return "Basic Register Allocator"; }
|
2010-10-23 07:09:15 +08:00
|
|
|
|
|
|
|
/// RABasic analysis usage.
|
2014-03-07 17:26:03 +08:00
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
2010-10-23 07:09:15 +08:00
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
void releaseMemory() override;
|
2010-10-23 07:09:15 +08:00
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
Spiller &spiller() override { return *SpillerInstance; }
|
2010-11-11 03:18:47 +08:00
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
void enqueue(LiveInterval *LI) override {
|
2011-02-23 07:01:52 +08:00
|
|
|
Queue.push(LI);
|
|
|
|
}
|
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
LiveInterval *dequeue() override {
|
2011-02-23 07:01:52 +08:00
|
|
|
if (Queue.empty())
|
2014-04-14 08:51:57 +08:00
|
|
|
return nullptr;
|
2011-02-23 07:01:52 +08:00
|
|
|
LiveInterval *LI = Queue.top();
|
|
|
|
Queue.pop();
|
|
|
|
return LI;
|
|
|
|
}
|
|
|
|
|
2014-03-07 17:26:03 +08:00
|
|
|
unsigned selectOrSplit(LiveInterval &VirtReg,
|
|
|
|
SmallVectorImpl<unsigned> &SplitVRegs) override;
|
2010-10-23 07:09:15 +08:00
|
|
|
|
|
|
|
/// Perform register allocation.
|
2014-03-07 17:26:03 +08:00
|
|
|
bool runOnMachineFunction(MachineFunction &mf) override;
|
2010-10-23 07:09:15 +08:00
|
|
|
|
2016-08-24 05:19:49 +08:00
|
|
|
MachineFunctionProperties getRequiredProperties() const override {
|
|
|
|
return MachineFunctionProperties().set(
|
|
|
|
MachineFunctionProperties::Property::NoPHIs);
|
|
|
|
}
|
|
|
|
|
2012-01-12 06:52:14 +08:00
|
|
|
// Helper for spilling all live virtual registers currently unified under preg
|
|
|
|
// that interfere with the most recently queried lvr. Return true if spilling
|
|
|
|
// was successful, and append any new spilled/split intervals to splitLVRs.
|
|
|
|
bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
|
2013-08-15 07:50:04 +08:00
|
|
|
SmallVectorImpl<unsigned> &SplitVRegs);
|
2012-01-12 06:52:14 +08:00
|
|
|
|
2010-10-23 07:09:15 +08:00
|
|
|
static char ID;
|
|
|
|
};
|
|
|
|
|
|
|
|
char RABasic::ID = 0;
|
|
|
|
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
2017-06-03 06:46:26 +08:00
|
|
|
char &llvm::RABasicID = RABasic::ID;
|
|
|
|
|
|
|
|
INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
|
|
|
|
false, false)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(LiveStacks)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
|
|
|
|
INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
|
|
|
|
false)
|
|
|
|
|
2017-06-03 06:46:31 +08:00
|
|
|
bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) {
|
2017-09-15 15:47:38 +08:00
|
|
|
LiveInterval &LI = LIS->getInterval(VirtReg);
|
2017-06-03 06:46:31 +08:00
|
|
|
if (VRM->hasPhys(VirtReg)) {
|
|
|
|
Matrix->unassign(LI);
|
|
|
|
aboutToRemoveInterval(LI);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
// Unassigned virtreg is probably in the priority queue.
|
|
|
|
// RegAllocBase will erase it after dequeueing.
|
2017-09-15 15:47:38 +08:00
|
|
|
// Nonetheless, clear the live-range so that the debug
|
|
|
|
// dump will show the right state for that VirtReg.
|
|
|
|
LI.clear();
|
2017-06-03 06:46:31 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) {
|
|
|
|
if (!VRM->hasPhys(VirtReg))
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Register is assigned, put it back on the queue for reassignment.
|
|
|
|
LiveInterval &LI = LIS->getInterval(VirtReg);
|
|
|
|
Matrix->unassign(LI);
|
|
|
|
enqueue(&LI);
|
|
|
|
}
|
|
|
|
|
2010-10-23 07:09:15 +08:00
|
|
|
RABasic::RABasic(): MachineFunctionPass(ID) {
|
|
|
|
}
|
|
|
|
|
2010-12-01 07:18:47 +08:00
|
|
|
void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
|
|
AU.setPreservesCFG();
|
[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.
This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:
- FunctionAAResults is a type-erasing alias analysis results aggregation
interface to walk a single query across a range of results from
different alias analyses. Currently this is function-specific as we
always assume that aliasing queries are *within* a function.
- AAResultBase is a CRTP utility providing stub implementations of
various parts of the alias analysis result concept, notably in several
cases in terms of other more general parts of the interface. This can
be used to implement only a narrow part of the interface rather than
the entire interface. This isn't really ideal, this logic should be
hoisted into FunctionAAResults as currently it will cause
a significant amount of redundant work, but it faithfully models the
behavior of the prior infrastructure.
- All the alias analysis passes are ported to be wrapper passes for the
legacy PM and new-style analysis passes for the new PM with a shared
result object. In some cases (most notably CFL), this is an extremely
naive approach that we should revisit when we can specialize for the
new pass manager.
- BasicAA has been restructured to reflect that it is much more
fundamentally a function analysis because it uses dominator trees and
loop info that need to be constructed for each function.
All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.
The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.
This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.
Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.
One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.
Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.
Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.
Differential Revision: http://reviews.llvm.org/D12080
llvm-svn: 247167
2015-09-10 01:55:00 +08:00
|
|
|
AU.addRequired<AAResultsWrapperPass>();
|
|
|
|
AU.addPreserved<AAResultsWrapperPass>();
|
2010-12-01 07:18:47 +08:00
|
|
|
AU.addRequired<LiveIntervals>();
|
2012-06-09 07:44:45 +08:00
|
|
|
AU.addPreserved<LiveIntervals>();
|
2010-12-01 07:18:47 +08:00
|
|
|
AU.addPreserved<SlotIndexes>();
|
2011-04-06 05:40:37 +08:00
|
|
|
AU.addRequired<LiveDebugVariables>();
|
|
|
|
AU.addPreserved<LiveDebugVariables>();
|
2010-12-01 07:18:47 +08:00
|
|
|
AU.addRequired<LiveStacks>();
|
|
|
|
AU.addPreserved<LiveStacks>();
|
2013-06-18 03:00:36 +08:00
|
|
|
AU.addRequired<MachineBlockFrequencyInfo>();
|
|
|
|
AU.addPreserved<MachineBlockFrequencyInfo>();
|
2010-12-01 07:18:47 +08:00
|
|
|
AU.addRequiredID(MachineDominatorsID);
|
|
|
|
AU.addPreservedID(MachineDominatorsID);
|
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
|
|
AU.addRequired<VirtRegMap>();
|
|
|
|
AU.addPreserved<VirtRegMap>();
|
2012-06-21 06:52:24 +08:00
|
|
|
AU.addRequired<LiveRegMatrix>();
|
|
|
|
AU.addPreserved<LiveRegMatrix>();
|
2010-12-01 07:18:47 +08:00
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
2010-10-23 07:09:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void RABasic::releaseMemory() {
|
2014-07-19 09:05:11 +08:00
|
|
|
SpillerInstance.reset();
|
2010-10-23 07:09:15 +08:00
|
|
|
}
|
|
|
|
|
2012-01-12 06:52:14 +08:00
|
|
|
|
|
|
|
// Spill or split all live virtual registers currently unified under PhysReg
|
|
|
|
// that interfere with VirtReg. The newly spilled or split live intervals are
|
|
|
|
// returned by appending them to SplitVRegs.
|
|
|
|
bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
|
2013-08-15 07:50:04 +08:00
|
|
|
SmallVectorImpl<unsigned> &SplitVRegs) {
|
2012-01-12 06:52:14 +08:00
|
|
|
// Record each interference and determine if all are spillable before mutating
|
|
|
|
// either the union or live intervals.
|
2012-06-21 06:52:24 +08:00
|
|
|
SmallVector<LiveInterval*, 8> Intfs;
|
|
|
|
|
2012-01-12 06:52:14 +08:00
|
|
|
// Collect interferences assigned to any alias of the physical register.
|
2012-06-21 06:52:24 +08:00
|
|
|
for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
|
|
|
|
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
|
|
|
|
Q.collectInterferingVRegs();
|
|
|
|
for (unsigned i = Q.interferingVRegs().size(); i; --i) {
|
|
|
|
LiveInterval *Intf = Q.interferingVRegs()[i - 1];
|
|
|
|
if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
|
|
|
|
return false;
|
|
|
|
Intfs.push_back(Intf);
|
2012-01-12 06:52:14 +08:00
|
|
|
}
|
|
|
|
}
|
2017-12-01 00:12:24 +08:00
|
|
|
DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
|
|
|
|
<< " interferences with " << VirtReg << "\n");
|
2012-06-21 06:52:24 +08:00
|
|
|
assert(!Intfs.empty() && "expected interference");
|
2012-01-12 06:52:14 +08:00
|
|
|
|
|
|
|
// Spill each interfering vreg allocated to PhysReg or an alias.
|
2012-06-21 06:52:24 +08:00
|
|
|
for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
|
|
|
|
LiveInterval &Spill = *Intfs[i];
|
|
|
|
|
|
|
|
// Skip duplicates.
|
|
|
|
if (!VRM->hasPhys(Spill.reg))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Deallocate the interfering vreg by removing it from the union.
|
|
|
|
// A LiveInterval instance may not be in a union during modification!
|
|
|
|
Matrix->unassign(Spill);
|
|
|
|
|
|
|
|
// Spill the extracted interval.
|
2017-06-03 06:46:31 +08:00
|
|
|
LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
|
2012-06-21 06:52:24 +08:00
|
|
|
spiller().spill(LRE);
|
|
|
|
}
|
2012-01-12 06:52:14 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-10-23 07:09:15 +08:00
|
|
|
// Driver for the register assignment and splitting heuristics.
|
|
|
|
// Manages iteration over the LiveIntervalUnions.
|
2010-11-20 10:43:55 +08:00
|
|
|
//
|
2010-12-01 07:18:47 +08:00
|
|
|
// This is a minimal implementation of register assignment and splitting that
|
|
|
|
// spills whenever we run out of registers.
|
2010-10-23 07:09:15 +08:00
|
|
|
//
|
|
|
|
// selectOrSplit can only be called once per live virtual register. We then do a
|
|
|
|
// single interference test for each register the correct class until we find an
|
|
|
|
// available register. So, the number of interference tests in the worst case is
|
|
|
|
// |vregs| * |machineregs|. And since the number of interference tests is
|
2010-12-01 07:18:47 +08:00
|
|
|
// minimal, there is no value in caching them outside the scope of
|
|
|
|
// selectOrSplit().
|
|
|
|
unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
|
2013-08-15 07:50:04 +08:00
|
|
|
SmallVectorImpl<unsigned> &SplitVRegs) {
|
2010-11-11 03:18:47 +08:00
|
|
|
// Populate a list of physical register spill candidates.
|
2010-12-01 07:18:47 +08:00
|
|
|
SmallVector<unsigned, 8> PhysRegSpillCands;
|
2010-11-09 02:02:08 +08:00
|
|
|
|
2010-11-20 10:43:55 +08:00
|
|
|
// Check for an available register in this class.
|
2015-07-16 06:16:00 +08:00
|
|
|
AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
|
2012-06-21 06:52:24 +08:00
|
|
|
while (unsigned PhysReg = Order.next()) {
|
|
|
|
// Check for interference in PhysReg
|
|
|
|
switch (Matrix->checkInterference(VirtReg, PhysReg)) {
|
|
|
|
case LiveRegMatrix::IK_Free:
|
|
|
|
// PhysReg is available, allocate it.
|
2010-12-01 07:18:47 +08:00
|
|
|
return PhysReg;
|
2010-11-11 03:18:47 +08:00
|
|
|
|
2012-06-21 06:52:24 +08:00
|
|
|
case LiveRegMatrix::IK_VirtReg:
|
|
|
|
// Only virtual registers in the way, we may be able to spill them.
|
2010-12-01 07:18:47 +08:00
|
|
|
PhysRegSpillCands.push_back(PhysReg);
|
2012-06-21 06:52:24 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
default:
|
|
|
|
// RegMask or RegUnit interference.
|
|
|
|
continue;
|
2010-11-09 02:02:08 +08:00
|
|
|
}
|
2010-10-23 07:09:15 +08:00
|
|
|
}
|
2012-06-21 06:52:24 +08:00
|
|
|
|
2010-11-11 03:18:47 +08:00
|
|
|
// Try to spill another interfering reg with less spill weight.
|
2010-12-01 07:18:47 +08:00
|
|
|
for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
|
2012-06-21 06:52:24 +08:00
|
|
|
PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
|
|
|
|
if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
|
|
|
|
continue;
|
2010-11-20 10:43:55 +08:00
|
|
|
|
2012-06-21 06:52:24 +08:00
|
|
|
assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
|
2010-12-08 02:51:27 +08:00
|
|
|
"Interference after spill.");
|
2010-11-11 03:18:47 +08:00
|
|
|
// Tell the caller to allocate to this newly freed physical register.
|
2010-12-01 07:18:47 +08:00
|
|
|
return *PhysRegI;
|
2010-11-09 02:02:08 +08:00
|
|
|
}
|
2011-05-07 05:58:30 +08:00
|
|
|
|
2010-12-01 07:18:47 +08:00
|
|
|
// No other spill candidates were found, so spill the current VirtReg.
|
|
|
|
DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
|
2011-05-07 05:58:30 +08:00
|
|
|
if (!VirtReg.isSpillable())
|
|
|
|
return ~0u;
|
2017-06-03 06:46:31 +08:00
|
|
|
LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
|
2011-03-10 09:51:42 +08:00
|
|
|
spiller().spill(LRE);
|
2010-11-20 10:43:55 +08:00
|
|
|
|
2010-11-11 03:18:47 +08:00
|
|
|
// The live virtual register requesting allocation was spilled, so tell
|
|
|
|
// the caller not to allocate anything during this round.
|
|
|
|
return 0;
|
2010-11-09 02:02:08 +08:00
|
|
|
}
|
2010-10-23 07:09:15 +08:00
|
|
|
|
|
|
|
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
|
|
|
|
DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
|
|
|
|
<< "********** Function: "
|
2012-08-23 01:18:53 +08:00
|
|
|
<< mf.getName() << '\n');
|
2010-10-23 07:09:15 +08:00
|
|
|
|
2010-12-01 07:18:47 +08:00
|
|
|
MF = &mf;
|
2012-06-21 06:52:29 +08:00
|
|
|
RegAllocBase::init(getAnalysis<VirtRegMap>(),
|
|
|
|
getAnalysis<LiveIntervals>(),
|
|
|
|
getAnalysis<LiveRegMatrix>());
|
2013-11-11 01:46:31 +08:00
|
|
|
|
2015-08-10 19:59:44 +08:00
|
|
|
calculateSpillWeightsAndHints(*LIS, *MF, VRM,
|
2013-11-12 03:04:45 +08:00
|
|
|
getAnalysis<MachineLoopInfo>(),
|
|
|
|
getAnalysis<MachineBlockFrequencyInfo>());
|
2013-11-11 01:46:31 +08:00
|
|
|
|
2011-04-01 07:02:17 +08:00
|
|
|
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
|
2010-11-20 10:43:55 +08:00
|
|
|
|
2010-10-27 02:34:01 +08:00
|
|
|
allocatePhysRegs();
|
2016-04-13 11:08:27 +08:00
|
|
|
postOptimization();
|
2010-10-23 07:09:15 +08:00
|
|
|
|
|
|
|
// Diagnostic output before rewriting
|
2010-12-01 07:18:47 +08:00
|
|
|
DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
|
2010-10-23 07:09:15 +08:00
|
|
|
|
2010-10-27 02:34:01 +08:00
|
|
|
releaseMemory();
|
2010-10-23 07:09:15 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-11-20 10:43:55 +08:00
|
|
|
FunctionPass* llvm::createBasicRegisterAllocator()
|
2010-10-23 07:09:15 +08:00
|
|
|
{
|
|
|
|
return new RABasic();
|
|
|
|
}
|