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llvm-project/llvm/test/CodeGen/X86/extract-store.ll

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[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
X86: Resolve a long standing FIXME and properly isel pextr[bw]. Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 200957
2014-02-07 08:16:33 +08:00
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
define void @extract_i8_0(i8* nocapture %dst, <16 x i8> %foo) {
; SSE2-LABEL: extract_i8_0:
; SSE2: # BB#0:
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-NEXT: movb %al, (%rdi)
; SSE2-NEXT: retq
;
; SSE41-LABEL: extract_i8_0:
; SSE41: # BB#0:
; SSE41-NEXT: pextrb $0, %xmm0, (%rdi)
; SSE41-NEXT: retq
;
; AVX-LABEL: extract_i8_0:
; AVX: # BB#0:
; AVX-NEXT: vpextrb $0, %xmm0, (%rdi)
; AVX-NEXT: retq
%vecext = extractelement <16 x i8> %foo, i32 0
store i8 %vecext, i8* %dst, align 1
ret void
}
define void @extract_i8_15(i8* nocapture %dst, <16 x i8> %foo) {
; SSE2-LABEL: extract_i8_15:
; SSE2: # BB#0:
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-NEXT: movb %al, (%rdi)
; SSE2-NEXT: retq
;
; SSE41-LABEL: extract_i8_15:
; SSE41: # BB#0:
; SSE41-NEXT: pextrb $15, %xmm0, (%rdi)
; SSE41-NEXT: retq
;
; AVX-LABEL: extract_i8_15:
; AVX: # BB#0:
; AVX-NEXT: vpextrb $15, %xmm0, (%rdi)
; AVX-NEXT: retq
X86: Resolve a long standing FIXME and properly isel pextr[bw]. Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 200957
2014-02-07 08:16:33 +08:00
%vecext = extractelement <16 x i8> %foo, i32 15
store i8 %vecext, i8* %dst, align 1
ret void
}
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
define void @extract_i16_0(i16* nocapture %dst, <8 x i16> %foo) {
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
2016-07-21 22:54:17 +08:00
; SSE2-LABEL: extract_i16_0:
; SSE2: # BB#0:
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: movw %ax, (%rdi)
; SSE2-NEXT: retq
;
; SSE41-LABEL: extract_i16_0:
; SSE41: # BB#0:
; SSE41-NEXT: pextrw $0, %xmm0, (%rdi)
; SSE41-NEXT: retq
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
;
; AVX-LABEL: extract_i16_0:
; AVX: # BB#0:
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
2016-07-21 22:54:17 +08:00
; AVX-NEXT: vpextrw $0, %xmm0, (%rdi)
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
; AVX-NEXT: retq
%vecext = extractelement <8 x i16> %foo, i32 0
store i16 %vecext, i16* %dst, align 1
ret void
}
define void @extract_i16_7(i16* nocapture %dst, <8 x i16> %foo) {
; SSE2-LABEL: extract_i16_7:
; SSE2: # BB#0:
; SSE2-NEXT: pextrw $7, %xmm0, %eax
; SSE2-NEXT: movw %ax, (%rdi)
; SSE2-NEXT: retq
;
; SSE41-LABEL: extract_i16_7:
; SSE41: # BB#0:
; SSE41-NEXT: pextrw $7, %xmm0, (%rdi)
; SSE41-NEXT: retq
;
; AVX-LABEL: extract_i16_7:
; AVX: # BB#0:
; AVX-NEXT: vpextrw $7, %xmm0, (%rdi)
; AVX-NEXT: retq
SelectionDAG: Handle out-of-bounds index in extract vector element Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size. Test Plan: CodeGen for X86 test included. Also one incorrect regression test fixed. Reviewers: qcolombet, chandlerc, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D9250 llvm-svn: 236584
2015-05-06 18:19:14 +08:00
%vecext = extractelement <8 x i16> %foo, i32 7
store i16 %vecext, i16* %dst, align 1
ret void
}
define void @extract_i8_undef(i8* nocapture %dst, <16 x i8> %foo) {
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
; SSE-LABEL: extract_i8_undef:
; SSE: # BB#0:
; SSE-NEXT: retq
;
; AVX-LABEL: extract_i8_undef:
; AVX: # BB#0:
; AVX-NEXT: retq
SelectionDAG: Handle out-of-bounds index in extract vector element Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size. Test Plan: CodeGen for X86 test included. Also one incorrect regression test fixed. Reviewers: qcolombet, chandlerc, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D9250 llvm-svn: 236584
2015-05-06 18:19:14 +08:00
%vecext = extractelement <16 x i8> %foo, i32 16 ; undef
store i8 %vecext, i8* %dst, align 1
ret void
}
define void @extract_i16_undef(i16* nocapture %dst, <8 x i16> %foo) {
[X86][SSE] Regenerate extraction+store memop tests Added tests for SSE2 as well as SSE41+AVX llvm-svn: 275876
2016-07-19 02:44:01 +08:00
; SSE-LABEL: extract_i16_undef:
; SSE: # BB#0:
; SSE-NEXT: retq
;
; AVX-LABEL: extract_i16_undef:
; AVX: # BB#0:
; AVX-NEXT: retq
SelectionDAG: Handle out-of-bounds index in extract vector element Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size. Test Plan: CodeGen for X86 test included. Also one incorrect regression test fixed. Reviewers: qcolombet, chandlerc, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D9250 llvm-svn: 236584
2015-05-06 18:19:14 +08:00
%vecext = extractelement <8 x i16> %foo, i32 9 ; undef
X86: Resolve a long standing FIXME and properly isel pextr[bw]. Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 200957
2014-02-07 08:16:33 +08:00
store i16 %vecext, i16* %dst, align 1
ret void
}