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llvm-project/llvm/test/CodeGen/Mips/madd-msub.ll

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[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32
; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,32R6
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64
; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64
; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64R6
; RUN: llc -march=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=ALL,16
[mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6 Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 llvm-svn: 210762
2014-06-12 18:54:16 +08:00
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: madd1:
; 32: # %bb.0: # %entry
; 32-NEXT: sra $1, $6, 31
; 32-NEXT: mtlo $6
; 32-NEXT: mthi $1
; 32-NEXT: madd $5, $4
; 32-NEXT: mfhi $2
; 32-NEXT: jr $ra
; 32-NEXT: mflo $3
;
; 32R6-LABEL: madd1:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $5, $4
; 32R6-NEXT: addu $3, $1, $6
; 32R6-NEXT: sltu $1, $3, $1
; 32R6-NEXT: muh $2, $5, $4
; 32R6-NEXT: sra $4, $6, 31
; 32R6-NEXT: addu $2, $2, $4
; 32R6-NEXT: jr $ra
; 32R6-NEXT: addu $2, $2, $1
;
; DSP-LABEL: madd1:
; DSP: # %bb.0: # %entry
; DSP-NEXT: sra $1, $6, 31
; DSP-NEXT: mtlo $6, $ac0
; DSP-NEXT: mthi $1, $ac0
; DSP-NEXT: madd $ac0, $5, $4
; DSP-NEXT: mfhi $2, $ac0
; DSP-NEXT: jr $ra
; DSP-NEXT: mflo $3, $ac0
;
; 64-LABEL: madd1:
; 64: # %bb.0: # %entry
; 64-NEXT: sll $1, $4, 0
; 64-NEXT: sll $2, $5, 0
; 64-NEXT: dmult $2, $1
; 64-NEXT: mflo $1
; 64-NEXT: sll $2, $6, 0
; 64-NEXT: jr $ra
; 64-NEXT: daddu $2, $1, $2
;
; 64R6-LABEL: madd1:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sll $1, $4, 0
; 64R6-NEXT: sll $2, $5, 0
; 64R6-NEXT: dmul $1, $2, $1
; 64R6-NEXT: sll $2, $6, 0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: daddu $2, $1, $2
;
; 16-LABEL: madd1:
; 16: # %bb.0: # %entry
; 16-NEXT: mult $5, $4
; 16-NEXT: mflo $2
; 16-NEXT: mfhi $3
; 16-NEXT: sra $4, $6, 31
; 16-NEXT: addu $4, $3, $4
; 16-NEXT: addu $3, $2, $6
; 16-NEXT: sltu $3, $2
; 16-NEXT: move $2, $24
; 16-NEXT: addu $2, $4, $2
; 16-NEXT: jrc $ra
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
entry:
%conv = sext i32 %a to i64
%conv2 = sext i32 %b to i64
%mul = mul nsw i64 %conv2, %conv
%conv4 = sext i32 %c to i64
%add = add nsw i64 %mul, %conv4
ret i64 %add
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i64 @madd2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: madd2:
; 32: # %bb.0: # %entry
; 32-NEXT: addiu $1, $zero, 0
; 32-NEXT: mtlo $6
; 32-NEXT: mthi $1
; 32-NEXT: maddu $5, $4
; 32-NEXT: mfhi $2
; 32-NEXT: jr $ra
; 32-NEXT: mflo $3
;
; 32R6-LABEL: madd2:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $5, $4
; 32R6-NEXT: addu $3, $1, $6
; 32R6-NEXT: sltu $1, $3, $1
; 32R6-NEXT: muhu $2, $5, $4
; 32R6-NEXT: jr $ra
; 32R6-NEXT: addu $2, $2, $1
;
; DSP-LABEL: madd2:
; DSP: # %bb.0: # %entry
; DSP-NEXT: addiu $1, $zero, 0
; DSP-NEXT: mtlo $6, $ac0
; DSP-NEXT: mthi $1, $ac0
; DSP-NEXT: maddu $ac0, $5, $4
; DSP-NEXT: mfhi $2, $ac0
; DSP-NEXT: jr $ra
; DSP-NEXT: mflo $3, $ac0
;
; 64-LABEL: madd2:
; 64: # %bb.0: # %entry
; 64-NEXT: dmult $5, $4
; 64-NEXT: mflo $1
; 64-NEXT: jr $ra
; 64-NEXT: daddu $2, $1, $6
;
; 64R6-LABEL: madd2:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: dmul $1, $5, $4
; 64R6-NEXT: jr $ra
; 64R6-NEXT: daddu $2, $1, $6
;
; 16-LABEL: madd2:
; 16: # %bb.0: # %entry
; 16-NEXT: multu $5, $4
; 16-NEXT: mflo $2
; 16-NEXT: mfhi $4
; 16-NEXT: addu $3, $2, $6
; 16-NEXT: sltu $3, $2
; 16-NEXT: move $2, $24
; 16-NEXT: addu $2, $4, $2
; 16-NEXT: jrc $ra
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
entry:
%conv = zext i32 %a to i64
%conv2 = zext i32 %b to i64
%mul = mul nsw i64 %conv2, %conv
%conv4 = zext i32 %c to i64
%add = add nsw i64 %mul, %conv4
ret i64 %add
}
define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: madd3:
; 32: # %bb.0: # %entry
; 32-NEXT: mtlo $7
; 32-NEXT: mthi $6
; 32-NEXT: madd $5, $4
; 32-NEXT: mfhi $2
; 32-NEXT: jr $ra
; 32-NEXT: mflo $3
;
; 32R6-LABEL: madd3:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $5, $4
; 32R6-NEXT: addu $3, $1, $7
; 32R6-NEXT: sltu $1, $3, $1
; 32R6-NEXT: muh $2, $5, $4
; 32R6-NEXT: addu $2, $2, $6
; 32R6-NEXT: jr $ra
; 32R6-NEXT: addu $2, $2, $1
;
; DSP-LABEL: madd3:
; DSP: # %bb.0: # %entry
; DSP-NEXT: mtlo $7, $ac0
; DSP-NEXT: mthi $6, $ac0
; DSP-NEXT: madd $ac0, $5, $4
; DSP-NEXT: mfhi $2, $ac0
; DSP-NEXT: jr $ra
; DSP-NEXT: mflo $3, $ac0
;
; 64-LABEL: madd3:
; 64: # %bb.0: # %entry
; 64-NEXT: sll $1, $4, 0
; 64-NEXT: sll $2, $5, 0
; 64-NEXT: dmult $2, $1
; 64-NEXT: mflo $1
; 64-NEXT: jr $ra
; 64-NEXT: daddu $2, $1, $6
;
; 64R6-LABEL: madd3:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sll $1, $4, 0
; 64R6-NEXT: sll $2, $5, 0
; 64R6-NEXT: dmul $1, $2, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: daddu $2, $1, $6
;
; 16-LABEL: madd3:
; 16: # %bb.0: # %entry
; 16-NEXT: mult $5, $4
; 16-NEXT: mflo $2
; 16-NEXT: mfhi $3
; 16-NEXT: addu $4, $3, $6
; 16-NEXT: addu $3, $2, $7
; 16-NEXT: sltu $3, $2
; 16-NEXT: move $2, $24
; 16-NEXT: addu $2, $4, $2
; 16-NEXT: jrc $ra
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
entry:
%conv = sext i32 %a to i64
%conv2 = sext i32 %b to i64
%mul = mul nsw i64 %conv2, %conv
%add = add nsw i64 %mul, %c
ret i64 %add
}
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
define i32 @madd4(i32 %a, i32 %b, i32 %c) {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: madd4:
; 32: # %bb.0: # %entry
; 32-NEXT: mul $1, $4, $5
; 32-NEXT: jr $ra
; 32-NEXT: addu $2, $6, $1
;
; 32R6-LABEL: madd4:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $4, $5
; 32R6-NEXT: jr $ra
; 32R6-NEXT: addu $2, $6, $1
;
; DSP-LABEL: madd4:
; DSP: # %bb.0: # %entry
; DSP-NEXT: mul $1, $4, $5
; DSP-NEXT: jr $ra
; DSP-NEXT: addu $2, $6, $1
;
; 64-LABEL: madd4:
; 64: # %bb.0: # %entry
; 64-NEXT: sll $1, $5, 0
; 64-NEXT: sll $2, $4, 0
; 64-NEXT: mul $1, $2, $1
; 64-NEXT: sll $2, $6, 0
; 64-NEXT: jr $ra
; 64-NEXT: addu $2, $2, $1
;
; 64R6-LABEL: madd4:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sll $1, $5, 0
; 64R6-NEXT: sll $2, $4, 0
; 64R6-NEXT: mul $1, $2, $1
; 64R6-NEXT: sll $2, $6, 0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: addu $2, $2, $1
;
; 16-LABEL: madd4:
; 16: # %bb.0: # %entry
; 16-NEXT: mult $4, $5
; 16-NEXT: mflo $2
; 16-NEXT: addu $2, $6, $2
; 16-NEXT: jrc $ra
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
entry:
%mul = mul nsw i32 %a, %b
%add = add nsw i32 %c, %mul
ret i32 %add
}
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: msub1:
; 32: # %bb.0: # %entry
; 32-NEXT: sra $1, $6, 31
; 32-NEXT: mtlo $6
; 32-NEXT: mthi $1
; 32-NEXT: msub $5, $4
; 32-NEXT: mfhi $2
; 32-NEXT: jr $ra
; 32-NEXT: mflo $3
;
; 32R6-LABEL: msub1:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $5, $4
; 32R6-NEXT: sltu $2, $6, $1
; 32R6-NEXT: muh $3, $5, $4
; 32R6-NEXT: sra $4, $6, 31
; 32R6-NEXT: subu $3, $4, $3
; 32R6-NEXT: subu $2, $3, $2
; 32R6-NEXT: jr $ra
; 32R6-NEXT: subu $3, $6, $1
;
; DSP-LABEL: msub1:
; DSP: # %bb.0: # %entry
; DSP-NEXT: sra $1, $6, 31
; DSP-NEXT: mtlo $6, $ac0
; DSP-NEXT: mthi $1, $ac0
; DSP-NEXT: msub $ac0, $5, $4
; DSP-NEXT: mfhi $2, $ac0
; DSP-NEXT: jr $ra
; DSP-NEXT: mflo $3, $ac0
;
; 64-LABEL: msub1:
; 64: # %bb.0: # %entry
; 64-NEXT: sll $1, $4, 0
; 64-NEXT: sll $2, $5, 0
; 64-NEXT: dmult $2, $1
; 64-NEXT: mflo $1
; 64-NEXT: sll $2, $6, 0
; 64-NEXT: jr $ra
; 64-NEXT: dsubu $2, $2, $1
;
; 64R6-LABEL: msub1:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sll $1, $4, 0
; 64R6-NEXT: sll $2, $5, 0
; 64R6-NEXT: dmul $1, $2, $1
; 64R6-NEXT: sll $2, $6, 0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: dsubu $2, $2, $1
;
; 16-LABEL: msub1:
; 16: # %bb.0: # %entry
; 16-NEXT: mult $5, $4
; 16-NEXT: mflo $2
; 16-NEXT: mfhi $4
; 16-NEXT: subu $3, $6, $2
; 16-NEXT: sltu $6, $2
; 16-NEXT: move $2, $24
; 16-NEXT: sra $5, $6, 31
; 16-NEXT: subu $4, $5, $4
; 16-NEXT: subu $2, $4, $2
; 16-NEXT: jrc $ra
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
entry:
%conv = sext i32 %c to i64
%conv2 = sext i32 %a to i64
%conv4 = sext i32 %b to i64
%mul = mul nsw i64 %conv4, %conv2
%sub = sub nsw i64 %conv, %mul
ret i64 %sub
}
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define i64 @msub2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: msub2:
; 32: # %bb.0: # %entry
; 32-NEXT: addiu $1, $zero, 0
; 32-NEXT: mtlo $6
; 32-NEXT: mthi $1
; 32-NEXT: msubu $5, $4
; 32-NEXT: mfhi $2
; 32-NEXT: jr $ra
; 32-NEXT: mflo $3
;
; 32R6-LABEL: msub2:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $5, $4
; 32R6-NEXT: sltu $2, $6, $1
; 32R6-NEXT: muhu $3, $5, $4
; 32R6-NEXT: negu $3, $3
; 32R6-NEXT: subu $2, $3, $2
; 32R6-NEXT: jr $ra
; 32R6-NEXT: subu $3, $6, $1
;
; DSP-LABEL: msub2:
; DSP: # %bb.0: # %entry
; DSP-NEXT: addiu $1, $zero, 0
; DSP-NEXT: mtlo $6, $ac0
; DSP-NEXT: mthi $1, $ac0
; DSP-NEXT: msubu $ac0, $5, $4
; DSP-NEXT: mfhi $2, $ac0
; DSP-NEXT: jr $ra
; DSP-NEXT: mflo $3, $ac0
;
; 64-LABEL: msub2:
; 64: # %bb.0: # %entry
; 64-NEXT: dmult $5, $4
; 64-NEXT: mflo $1
; 64-NEXT: jr $ra
; 64-NEXT: dsubu $2, $6, $1
;
; 64R6-LABEL: msub2:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: dmul $1, $5, $4
; 64R6-NEXT: jr $ra
; 64R6-NEXT: dsubu $2, $6, $1
;
; 16-LABEL: msub2:
; 16: # %bb.0: # %entry
; 16-NEXT: multu $5, $4
; 16-NEXT: mflo $2
; 16-NEXT: mfhi $4
; 16-NEXT: subu $3, $6, $2
; 16-NEXT: sltu $6, $2
; 16-NEXT: move $2, $24
; 16-NEXT: neg $4, $4
; 16-NEXT: subu $2, $4, $2
; 16-NEXT: jrc $ra
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
entry:
%conv = zext i32 %c to i64
%conv2 = zext i32 %a to i64
%conv4 = zext i32 %b to i64
%mul = mul nsw i64 %conv4, %conv2
%sub = sub nsw i64 %conv, %mul
ret i64 %sub
}
define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: msub3:
; 32: # %bb.0: # %entry
; 32-NEXT: mtlo $7
; 32-NEXT: mthi $6
; 32-NEXT: msub $5, $4
; 32-NEXT: mfhi $2
; 32-NEXT: jr $ra
; 32-NEXT: mflo $3
;
; 32R6-LABEL: msub3:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $5, $4
; 32R6-NEXT: sltu $2, $7, $1
; 32R6-NEXT: muh $3, $5, $4
; 32R6-NEXT: subu $3, $6, $3
; 32R6-NEXT: subu $2, $3, $2
; 32R6-NEXT: jr $ra
; 32R6-NEXT: subu $3, $7, $1
;
; DSP-LABEL: msub3:
; DSP: # %bb.0: # %entry
; DSP-NEXT: mtlo $7, $ac0
; DSP-NEXT: mthi $6, $ac0
; DSP-NEXT: msub $ac0, $5, $4
; DSP-NEXT: mfhi $2, $ac0
; DSP-NEXT: jr $ra
; DSP-NEXT: mflo $3, $ac0
;
; 64-LABEL: msub3:
; 64: # %bb.0: # %entry
; 64-NEXT: sll $1, $4, 0
; 64-NEXT: sll $2, $5, 0
; 64-NEXT: dmult $2, $1
; 64-NEXT: mflo $1
; 64-NEXT: jr $ra
; 64-NEXT: dsubu $2, $6, $1
;
; 64R6-LABEL: msub3:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sll $1, $4, 0
; 64R6-NEXT: sll $2, $5, 0
; 64R6-NEXT: dmul $1, $2, $1
; 64R6-NEXT: jr $ra
; 64R6-NEXT: dsubu $2, $6, $1
;
; 16-LABEL: msub3:
; 16: # %bb.0: # %entry
; 16-NEXT: mult $5, $4
; 16-NEXT: mflo $2
; 16-NEXT: mfhi $4
; 16-NEXT: subu $3, $7, $2
; 16-NEXT: sltu $7, $2
; 16-NEXT: move $2, $24
; 16-NEXT: subu $4, $6, $4
; 16-NEXT: subu $2, $4, $2
; 16-NEXT: jrc $ra
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka llvm-svn: 123760
2011-01-19 03:29:17 +08:00
entry:
%conv = sext i32 %a to i64
%conv3 = sext i32 %b to i64
%mul = mul nsw i64 %conv3, %conv
%sub = sub nsw i64 %c, %mul
ret i64 %sub
}
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
define i32 @msub4(i32 %a, i32 %b, i32 %c) {
[NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch llvm-svn: 361860
2019-05-29 02:31:36 +08:00
; 32-LABEL: msub4:
; 32: # %bb.0: # %entry
; 32-NEXT: mul $1, $4, $5
; 32-NEXT: jr $ra
; 32-NEXT: subu $2, $6, $1
;
; 32R6-LABEL: msub4:
; 32R6: # %bb.0: # %entry
; 32R6-NEXT: mul $1, $4, $5
; 32R6-NEXT: jr $ra
; 32R6-NEXT: subu $2, $6, $1
;
; DSP-LABEL: msub4:
; DSP: # %bb.0: # %entry
; DSP-NEXT: mul $1, $4, $5
; DSP-NEXT: jr $ra
; DSP-NEXT: subu $2, $6, $1
;
; 64-LABEL: msub4:
; 64: # %bb.0: # %entry
; 64-NEXT: sll $1, $5, 0
; 64-NEXT: sll $2, $4, 0
; 64-NEXT: mul $1, $2, $1
; 64-NEXT: sll $2, $6, 0
; 64-NEXT: jr $ra
; 64-NEXT: subu $2, $2, $1
;
; 64R6-LABEL: msub4:
; 64R6: # %bb.0: # %entry
; 64R6-NEXT: sll $1, $5, 0
; 64R6-NEXT: sll $2, $4, 0
; 64R6-NEXT: mul $1, $2, $1
; 64R6-NEXT: sll $2, $6, 0
; 64R6-NEXT: jr $ra
; 64R6-NEXT: subu $2, $2, $1
;
; 16-LABEL: msub4:
; 16: # %bb.0: # %entry
; 16-NEXT: mult $4, $5
; 16-NEXT: mflo $2
; 16-NEXT: subu $2, $6, $2
; 16-NEXT: jrc $ra
Reland "[mips] Fix multiprecision arithmetic." For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
2017-07-13 19:28:05 +08:00
entry:
%mul = mul nsw i32 %a, %b
%sub = sub nsw i32 %c, %mul
ret i32 %sub
}