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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

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AMDGPU/GlobalISel: Mark i32->i64 zext as legal llvm-svn: 326481
2018-03-02 04:56:21 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[globalisel] Remove redundant -global-isel option from tests that use -run-pass. NFC As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the -global-isel option is redundant when -run-pass is given. -global-isel sets up the GlobalISel passes in the pass manager but -run-pass skips that entirely and configures it's own pipeline. llvm-svn: 331603
2018-05-06 05:19:59 +08:00
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
AMDGPU/GlobalISel: Mark i32->i64 zext as legal llvm-svn: 326481
2018-03-02 04:56:21 +08:00
---
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
name: test_zext_s32_to_s64
AMDGPU/GlobalISel: Mark i32->i64 zext as legal llvm-svn: 326481
2018-03-02 04:56:21 +08:00
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
AMDGPU/GlobalISel: Mark i32->i64 zext as legal llvm-svn: 326481
2018-03-02 04:56:21 +08:00
liveins: $vgpr0
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
; CHECK-LABEL: name: test_zext_s32_to_s64
AMDGPU/GlobalISel: Mark i32->i64 zext as legal llvm-svn: 326481
2018-03-02 04:56:21 +08:00
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
AMDGPU/GlobalISel: Mark i32->i64 zext as legal llvm-svn: 326481
2018-03-02 04:56:21 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_ZEXT %0
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
$vgpr0_vgpr1 = COPY %1
...
---
name: test_zext_s16_to_s64
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s64) = G_ZEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: test_zext_s16_to_s32
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...
AMDGPU/GlobalISel: Clamp G_ZEXT source sizes Also clamps G_SEXT/G_ANYEXT, but the implementation is more limited so fewer cases actually work.
2020-01-10 22:06:47 +08:00
---
name: test_zext_s24_to_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s24_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
---
name: test_zext_i1_to_s32
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
AMDGPU/GlobalISel: Cleanup legality for extensions llvm-svn: 351691
2019-01-21 02:34:24 +08:00
; CHECK-LABEL: name: test_zext_i1_to_s32
[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms. There are two main issues preventing us from generating immediate form shifts: 1) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift immediate forms, but they currently don't work because the amount type is expected to be an s64 constant, but we only legalize them to have homogenous types. To deal with this, first we introduce a custom legalizer to *only* custom legalize s32 shifts which have a constant operand into a s64. There is also an additional artifact combiner to fold zexts(g_constant) to a larger G_CONSTANT if it's legal, a counterpart to the anyext version committed in an earlier patch. 2) For G_SHL the importer can't cope with the pattern. For this I introduced an early selection phase in the arm64 selector to select these forms manually before the tablegen selector pessimizes it to a register-register variant. Differential Revision: https://reviews.llvm.org/D63910 llvm-svn: 364994
2019-07-03 09:49:06 +08:00
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: $vgpr0 = COPY [[C]](s32)
AMDGPU/GlobalISel: Really legalize exts from i1 There is a combine that was hiding these tests not actually testing what they should be, although they were producing the expected end result. llvm-svn: 351698
2019-01-21 03:28:20 +08:00
%0:_(s1) = G_CONSTANT i1 0
%1:_(s32) = G_ZEXT %0
$vgpr0 = COPY %1
...
---
name: test_zext_i1_to_i64
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
AMDGPU/GlobalISel: Really legalize exts from i1 There is a combine that was hiding these tests not actually testing what they should be, although they were producing the expected end result. llvm-svn: 351698
2019-01-21 03:28:20 +08:00
; CHECK-LABEL: name: test_zext_i1_to_i64
[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms. There are two main issues preventing us from generating immediate form shifts: 1) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift immediate forms, but they currently don't work because the amount type is expected to be an s64 constant, but we only legalize them to have homogenous types. To deal with this, first we introduce a custom legalizer to *only* custom legalize s32 shifts which have a constant operand into a s64. There is also an additional artifact combiner to fold zexts(g_constant) to a larger G_CONSTANT if it's legal, a counterpart to the anyext version committed in an earlier patch. 2) For G_SHL the importer can't cope with the pattern. For this I introduced an early selection phase in the arm64 selector to select these forms manually before the tablegen selector pessimizes it to a register-register variant. Differential Revision: https://reviews.llvm.org/D63910 llvm-svn: 364994
2019-07-03 09:49:06 +08:00
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64)
AMDGPU/GlobalISel: Really legalize exts from i1 There is a combine that was hiding these tests not actually testing what they should be, although they were producing the expected end result. llvm-svn: 351698
2019-01-21 03:28:20 +08:00
%0:_(s1) = G_CONSTANT i1 0
%1:_(s64) = G_ZEXT %0
$vgpr0_vgpr1 = COPY %1
AMDGPU/GlobalISel: Mark i32->i64 zext as legal llvm-svn: 326481
2018-03-02 04:56:21 +08:00
...
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
---
name: test_zext_v2s16_to_v2s32
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_v2s16_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
GlobalISel: Lower scalarizing unmerge of a vector to shifts AMDGPU sometimes has legal s16 and <2 x s16> operations, but all registers are really 32-bit. An unmerge destination really should ben widened to a 32-bit register. If widening a scalarizing vector with a target size that matches the vector size, bitcast to integer and extract the relevant bits with shifts. I'm not sure if this is the right place for this. This could arguably be part of widenScalar for the result. I also have a growing feeling that we're missing a bitcast legalize action. llvm-svn: 367604
2019-08-02 03:10:05 +08:00
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s32>) = G_ZEXT %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_zext_v3s16_to_v3s32
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
liveins: $vgpr0_vgpr1
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
; CHECK-LABEL: name: test_zext_v3s16_to_v3s32
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
GlobalISel: Implement moreElementsVector for G_UNMERGE_VALUES sources This is necessary for handling <3 x s16> on AMDGPU, assuming this should be handled as 2 separate legalization actions. The alternative would be for fewerElementsVector to handle 3->2. llvm-svn: 369547
2019-08-22 00:59:10 +08:00
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<3 x s16>) = G_EXTRACT %0, 0
%2:_(<3 x s32>) = G_ZEXT %1
$vgpr0_vgpr1_vgpr2 = COPY %2
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
...
---
name: test_zext_v4s16_to_v4s32
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
liveins: $vgpr0_vgpr1
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
; CHECK-LABEL: name: test_zext_v4s16_to_v4s32
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES Odd sized vectors aren't handled yet. llvm-svn: 368713
2019-08-14 00:26:28 +08:00
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
%1:_(<4 x s32>) = G_ZEXT %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
---
name: test_zext_v2s32_to_v2s64
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_v2s32_to_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s64>) = G_ZEXT %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
---
name: test_zext_v3s32_to_v3s64
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: test_zext_v3s32_to_v3s64
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64)
; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s64>) = G_ZEXT %0
S_NOP 0, implicit %1
...
---
name: test_zext_v4s32_to_v4s64
body: |
AMDGPU/GlobalISel: Don't use g_implicit_def in a few tests llvm-svn: 353443
2019-02-08 02:33:22 +08:00
bb.0:
GlobalISel: Implement fewerElementsVector for extensions llvm-svn: 352155
2019-01-25 10:36:32 +08:00
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_zext_v4s32_to_v4s64
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[UV3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64), [[ZEXT3]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<4 x s64>) = G_ZEXT %0
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
...
AMDGPU/GlobalISel: Clamp G_ZEXT source sizes Also clamps G_SEXT/G_ANYEXT, but the implementation is more limited so fewer cases actually work.
2020-01-10 22:06:47 +08:00
---
name: test_zext_s8_to_s16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s8_to_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; CHECK: S_ENDPGM 0, implicit [[AND]](s16)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s16) = G_ZEXT %1
S_ENDPGM 0, implicit %2
...
---
name: test_zext_s8_to_s24
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s8_to_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[AND]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s24)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s24) = G_ZEXT %1
S_ENDPGM 0, implicit %2
...
---
name: test_zext_s7_to_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s7_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: S_ENDPGM 0, implicit [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1
S_ENDPGM 0, implicit %2
...
---
name: test_zext_s8_to_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: S_ENDPGM 0, implicit [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1
S_ENDPGM 0, implicit %2
...
---
name: test_zext_s32_to_s128
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s32_to_s128
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s128)
%0:_(s32) = COPY $vgpr0
%1:_(s128) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
---
name: test_zext_s32_to_s256
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s32_to_s256
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s256)
%0:_(s32) = COPY $vgpr0
%1:_(s256) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
---
name: test_zext_s32_to_s512
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s32_to_s512
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s512)
%0:_(s32) = COPY $vgpr0
%1:_(s512) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
---
name: test_zext_s32_to_s1024
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_s32_to_s1024
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s1024)
%0:_(s32) = COPY $vgpr0
%1:_(s1024) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
---
name: test_zext_s64_to_s128
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_s64_to_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64)
; CHECK: S_ENDPGM 0, implicit [[MV]](s128)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s128) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
---
name: test_zext_s64_to_s256
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_s64_to_s256
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64), [[C]](s64)
; CHECK: S_ENDPGM 0, implicit [[MV]](s256)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s256) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
---
name: test_zext_s64_to_s512
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_s64_to_s512
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64)
; CHECK: S_ENDPGM 0, implicit [[MV]](s512)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s512) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
---
name: test_zext_s64_to_s1024
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_s64_to_s1024
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64), [[C]](s64)
; CHECK: S_ENDPGM 0, implicit [[MV]](s1024)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s1024) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...
# ---
# name: test_zext_s96_to_s128
# body: |
# bb.0:
# liveins: $vgpr0_vgpr1_vgpr2
# %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
# %1:_(s128) = G_ZEXT %0
# S_ENDPGM 0, implicit %1
# ...
---
name: test_zext_s128_to_s256
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_zext_s128_to_s256
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](s64), [[C]](s64)
; CHECK: [[MV1:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s128), [[MV]](s128)
; CHECK: S_ENDPGM 0, implicit [[MV1]](s256)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s256) = G_ZEXT %0
S_ENDPGM 0, implicit %1
...