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llvm-project/llvm/test/CodeGen/X86/zext-inreg-1.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290
2009-09-09 07:54:48 +08:00
; RUN: llc < %s -march=x86 | not grep and
Reapply r54147 with a constraint to only use the 8-bit subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
2008-07-31 02:09:17 +08:00
; These tests differ from the ones in zext-inreg-0.ll in that
; on x86-64 they do require and instructions.
; These should use movzbl instead of 'and 255'.
; This related to not having ZERO_EXTEND_REG node.
Add an extra example that shouldn't get an and instruction. llvm-svn: 54443
2008-08-07 10:23:06 +08:00
define i64 @l(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 1099511627775
ret i64 %retval
}
define i64 @m(i64 %d) nounwind {
Reapply r54147 with a constraint to only use the 8-bit subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. llvm-svn: 54223
2008-07-31 02:09:17 +08:00
%e = add i64 %d, 1
%retval = and i64 %e, 281474976710655
ret i64 %retval
}