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llvm-project/llvm/test/CodeGen/X86/xor.ll

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[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s -check-prefixes=X32
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s -check-prefixes=X64,X64-LIN
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s -check-prefixes=X64,X64-WIN
convert testcases to filecheck. llvm-svn: 82759
2009-09-25 14:49:41 +08:00
; Though it is undefined, we want xor undef,undef to produce zero.
define <4 x i32> @test1() nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; X32-LABEL: test1:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32: # %bb.0:
; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: test1:
; X64: # %bb.0:
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: retq
%tmp = xor <4 x i32> undef, undef
ret <4 x i32> %tmp
convert testcases to filecheck. llvm-svn: 82759
2009-09-25 14:49:41 +08:00
}
; Though it is undefined, we want xor undef,undef to produce zero.
define i32 @test2() nounwind{
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; X32-LABEL: test2:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32: # %bb.0:
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: retl
;
; X64-LABEL: test2:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
%tmp = xor i32 undef, undef
ret i32 %tmp
convert testcases to filecheck. llvm-svn: 82759
2009-09-25 14:49:41 +08:00
}
define i32 @test3(i32 %a, i32 %b) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; X32-LABEL: test3:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: notl %eax
; X32-NEXT: andl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shrl %eax
; X32-NEXT: retl
;
; X64-LIN-LABEL: test3:
; X64-LIN: # %bb.0: # %entry
; X64-LIN-NEXT: movl %esi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: notl %eax
; X64-LIN-NEXT: andl %edi, %eax
; X64-LIN-NEXT: shrl %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test3:
; X64-WIN: # %bb.0: # %entry
; X64-WIN-NEXT: movl %edx, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: notl %eax
; X64-WIN-NEXT: andl %ecx, %eax
; X64-WIN-NEXT: shrl %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: retq
entry:
%tmp1not = xor i32 %b, -2
%tmp3 = and i32 %tmp1not, %a
%tmp4 = lshr i32 %tmp3, 1
ret i32 %tmp4
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
}
convert testcases to filecheck. llvm-svn: 82759
2009-09-25 14:49:41 +08:00
define i32 @test4(i32 %a, i32 %b) nounwind {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test4:
; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB3_1: # %bb
; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: xorl %ecx, %eax
; X32-NEXT: movl %eax, %edx
; X32-NEXT: notl %edx
; X32-NEXT: andl %ecx, %edx
; X32-NEXT: addl %edx, %edx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: jne .LBB3_1
; X32-NEXT: # %bb.2: # %bb12
; X32-NEXT: retl
;
; X64-LIN-LABEL: test4:
; X64-LIN: # %bb.0: # %entry
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: movl %edi, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: .p2align 4, 0x90
; X64-LIN-NEXT: .LBB3_1: # %bb
; X64-LIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: xorl %esi, %eax
; X64-LIN-NEXT: movl %eax, %ecx
; X64-LIN-NEXT: notl %ecx
; X64-LIN-NEXT: andl %esi, %ecx
; X64-LIN-NEXT: addl %ecx, %ecx
; X64-LIN-NEXT: movl %ecx, %esi
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: jne .LBB3_1
; X64-LIN-NEXT: # %bb.2: # %bb12
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test4:
; X64-WIN: # %bb.0: # %entry
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: movl %ecx, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: .p2align 4, 0x90
; X64-WIN-NEXT: .LBB3_1: # %bb
; X64-WIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: xorl %edx, %eax
; X64-WIN-NEXT: movl %eax, %ecx
; X64-WIN-NEXT: notl %ecx
; X64-WIN-NEXT: andl %edx, %ecx
; X64-WIN-NEXT: addl %ecx, %ecx
; X64-WIN-NEXT: movl %ecx, %edx
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: jne .LBB3_1
; X64-WIN-NEXT: # %bb.2: # %bb12
; X64-WIN-NEXT: retq
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
entry:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
br label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
%b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
%a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
%tmp3 = xor i32 %a_addr.0, %b_addr.0
%tmp4not = xor i32 %tmp3, 2147483647
%tmp6 = and i32 %tmp4not, %b_addr.0
%tmp8 = shl i32 %tmp6, 1
%tmp10 = icmp eq i32 %tmp8, 0
br i1 %tmp10, label %bb12, label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb12:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
ret i32 %tmp3
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
}
convert testcases to filecheck. llvm-svn: 82759
2009-09-25 14:49:41 +08:00
define i16 @test5(i16 %a, i16 %b) nounwind {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test5:
; X32: # %bb.0: # %entry
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB4_1: # %bb
; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: xorl %ecx, %eax
; X32-NEXT: movl %eax, %edx
; X32-NEXT: notl %edx
; X32-NEXT: andl %ecx, %edx
; X32-NEXT: addl %edx, %edx
; X32-NEXT: testw %dx, %dx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: jne .LBB4_1
; X32-NEXT: # %bb.2: # %bb12
; X32-NEXT: # kill: def $ax killed $ax killed $eax
; X32-NEXT: retl
;
; X64-LIN-LABEL: test5:
; X64-LIN: # %bb.0: # %entry
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: movl %edi, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: .p2align 4, 0x90
; X64-LIN-NEXT: .LBB4_1: # %bb
; X64-LIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: xorl %esi, %eax
; X64-LIN-NEXT: movl %eax, %ecx
; X64-LIN-NEXT: notl %ecx
; X64-LIN-NEXT: andl %esi, %ecx
; X64-LIN-NEXT: addl %ecx, %ecx
; X64-LIN-NEXT: testw %cx, %cx
; X64-LIN-NEXT: movl %ecx, %esi
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: jne .LBB4_1
; X64-LIN-NEXT: # %bb.2: # %bb12
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: # kill: def $ax killed $ax killed $eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test5:
; X64-WIN: # %bb.0: # %entry
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32 Summary: Re-lands r328386 and r328443, reverting r328482. Incorporates fixes from @mstorsjo in D44876 (thanks!) so that small parameters in i8 and i16 do not end up in the SysV register parameters (EDI, ESI, etc). I added tests for how we receive small parameters, since that is the important part. It's always safe to store more bytes than will be read, but the assumptions you make when loading them are what really matter. I also tested this by self-hosting clang and it passed tests on win64. Reviewers: mstorsjo, hans Subscribers: hiraditya, mstorsjo, llvm-commits Differential Revision: https://reviews.llvm.org/D44900 llvm-svn: 328570
2018-03-27 02:49:48 +08:00
; X64-WIN-NEXT: # kill: def $dx killed $dx def $edx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: movl %ecx, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: .p2align 4, 0x90
; X64-WIN-NEXT: .LBB4_1: # %bb
; X64-WIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: xorl %edx, %eax
; X64-WIN-NEXT: movl %eax, %ecx
; X64-WIN-NEXT: notl %ecx
; X64-WIN-NEXT: andl %edx, %ecx
; X64-WIN-NEXT: addl %ecx, %ecx
; X64-WIN-NEXT: testw %cx, %cx
; X64-WIN-NEXT: movl %ecx, %edx
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: jne .LBB4_1
; X64-WIN-NEXT: # %bb.2: # %bb12
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: # kill: def $ax killed $ax killed $eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: retq
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
entry:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
br label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
%b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
%a_addr.0 = phi i16 [ %a, %entry ], [ %tmp3, %bb ]
%tmp3 = xor i16 %a_addr.0, %b_addr.0
%tmp4not = xor i16 %tmp3, 32767
%tmp6 = and i16 %tmp4not, %b_addr.0
%tmp8 = shl i16 %tmp6, 1
%tmp10 = icmp eq i16 %tmp8, 0
br i1 %tmp10, label %bb12, label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb12:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
ret i16 %tmp3
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
}
convert testcases to filecheck. llvm-svn: 82759
2009-09-25 14:49:41 +08:00
define i8 @test6(i8 %a, i8 %b) nounwind {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test6:
; X32: # %bb.0: # %entry
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB5_1: # %bb
; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: xorb %cl, %al
; X32-NEXT: movl %eax, %edx
; X32-NEXT: notb %dl
; X32-NEXT: andb %cl, %dl
; X32-NEXT: addb %dl, %dl
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: jne .LBB5_1
; X32-NEXT: # %bb.2: # %bb12
; X32-NEXT: retl
;
; X64-LIN-LABEL: test6:
; X64-LIN: # %bb.0: # %entry
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: movl %edi, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: .p2align 4, 0x90
; X64-LIN-NEXT: .LBB5_1: # %bb
; X64-LIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: xorb %sil, %al
; X64-LIN-NEXT: movl %eax, %ecx
; X64-LIN-NEXT: notb %cl
; X64-LIN-NEXT: andb %sil, %cl
; X64-LIN-NEXT: addb %cl, %cl
; X64-LIN-NEXT: movl %ecx, %esi
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: jne .LBB5_1
; X64-LIN-NEXT: # %bb.2: # %bb12
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: # kill: def $al killed $al killed $eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test6:
; X64-WIN: # %bb.0: # %entry
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: movl %ecx, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: .p2align 4, 0x90
; X64-WIN-NEXT: .LBB5_1: # %bb
; X64-WIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: xorb %dl, %al
; X64-WIN-NEXT: movl %eax, %ecx
; X64-WIN-NEXT: notb %cl
; X64-WIN-NEXT: andb %dl, %cl
; X64-WIN-NEXT: addb %cl, %cl
; X64-WIN-NEXT: movl %ecx, %edx
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: jne .LBB5_1
; X64-WIN-NEXT: # %bb.2: # %bb12
; X64-WIN-NEXT: retq
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
entry:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
br label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
%b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
%a_addr.0 = phi i8 [ %a, %entry ], [ %tmp3, %bb ]
%tmp3 = xor i8 %a_addr.0, %b_addr.0
%tmp4not = xor i8 %tmp3, 127
%tmp6 = and i8 %tmp4not, %b_addr.0
%tmp8 = shl i8 %tmp6, 1
%tmp10 = icmp eq i8 %tmp8, 0
br i1 %tmp10, label %bb12, label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb12:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
ret i8 %tmp3
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
}
convert testcases to filecheck. llvm-svn: 82759
2009-09-25 14:49:41 +08:00
define i32 @test7(i32 %a, i32 %b) nounwind {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test7:
; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB6_1: # %bb
; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: xorl %ecx, %eax
; X32-NEXT: movl %eax, %edx
; X32-NEXT: xorl $2147483646, %edx # imm = 0x7FFFFFFE
; X32-NEXT: andl %ecx, %edx
; X32-NEXT: addl %edx, %edx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: jne .LBB6_1
; X32-NEXT: # %bb.2: # %bb12
; X32-NEXT: retl
;
; X64-LIN-LABEL: test7:
; X64-LIN: # %bb.0: # %entry
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: movl %edi, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: .p2align 4, 0x90
; X64-LIN-NEXT: .LBB6_1: # %bb
; X64-LIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: xorl %esi, %eax
; X64-LIN-NEXT: movl %eax, %ecx
; X64-LIN-NEXT: xorl $2147483646, %ecx # imm = 0x7FFFFFFE
; X64-LIN-NEXT: andl %esi, %ecx
; X64-LIN-NEXT: addl %ecx, %ecx
; X64-LIN-NEXT: movl %ecx, %esi
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: jne .LBB6_1
; X64-LIN-NEXT: # %bb.2: # %bb12
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test7:
; X64-WIN: # %bb.0: # %entry
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: movl %ecx, %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: .p2align 4, 0x90
; X64-WIN-NEXT: .LBB6_1: # %bb
; X64-WIN-NEXT: # =>This Inner Loop Header: Depth=1
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: xorl %edx, %eax
; X64-WIN-NEXT: movl %eax, %ecx
; X64-WIN-NEXT: xorl $2147483646, %ecx # imm = 0x7FFFFFFE
; X64-WIN-NEXT: andl %edx, %ecx
; X64-WIN-NEXT: addl %ecx, %ecx
; X64-WIN-NEXT: movl %ecx, %edx
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: jne .LBB6_1
; X64-WIN-NEXT: # %bb.2: # %bb12
; X64-WIN-NEXT: retq
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
entry:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
br label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
%b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
%a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
%tmp3 = xor i32 %a_addr.0, %b_addr.0
%tmp4not = xor i32 %tmp3, 2147483646
%tmp6 = and i32 %tmp4not, %b_addr.0
%tmp8 = shl i32 %tmp6, 1
%tmp10 = icmp eq i32 %tmp8, 0
br i1 %tmp10, label %bb12, label %bb
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
bb12:
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
ret i32 %tmp3
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
}
Canonicalize -1 - x to ~x. Instcombine does this but apparently there are situations where this pattern will escape the optimizer and / or created by isel. Here is a case that's seen in JavaScriptCore: %t1 = sub i32 0, %a %t2 = add i32 %t1, -1 The dag combiner pattern: ((c1-A)+c2) -> (c1+c2)-A will fold it to -1 - %a. llvm-svn: 93773
2010-01-19 05:38:44 +08:00
; rdar://7553032
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
define i32 @test8(i32 %a) nounwind {
; X32-LABEL: test8:
; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: notl %eax
; X32-NEXT: retl
;
; X64-LIN-LABEL: test8:
; X64-LIN: # %bb.0: # %entry
; X64-LIN-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: notl %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test8:
; X64-WIN: # %bb.0: # %entry
; X64-WIN-NEXT: movl %ecx, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: notl %eax
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: retq
Canonicalize -1 - x to ~x. Instcombine does this but apparently there are situations where this pattern will escape the optimizer and / or created by isel. Here is a case that's seen in JavaScriptCore: %t1 = sub i32 0, %a %t2 = add i32 %t1, -1 The dag combiner pattern: ((c1-A)+c2) -> (c1+c2)-A will fold it to -1 - %a. llvm-svn: 93773
2010-01-19 05:38:44 +08:00
entry:
%t1 = sub i32 0, %a
%t2 = add i32 %t1, -1
ret i32 %t2
}
DAGCombiner: Simplify inverted bit tests Fold (xor (and x, y), y) -> (and (not x), y) This removes an opportunity for a constant to appear twice. llvm-svn: 181395
2013-05-08 14:44:42 +08:00
define i32 @test9(i32 %a) nounwind {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test9:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: notl %eax
; X32-NEXT: andl $4096, %eax # imm = 0x1000
; X32-NEXT: retl
;
; X64-LIN-LABEL: test9:
; X64-LIN: # %bb.0:
; X64-LIN-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: notl %eax
; X64-LIN-NEXT: andl $4096, %eax # imm = 0x1000
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test9:
; X64-WIN: # %bb.0:
; X64-WIN-NEXT: movl %ecx, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-WIN-NEXT: notl %eax
; X64-WIN-NEXT: andl $4096, %eax # imm = 0x1000
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: retq
DAGCombiner: Simplify inverted bit tests Fold (xor (and x, y), y) -> (and (not x), y) This removes an opportunity for a constant to appear twice. llvm-svn: 181395
2013-05-08 14:44:42 +08:00
%1 = and i32 %a, 4096
%2 = xor i32 %1, 4096
ret i32 %2
}
DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)). PR15948. llvm-svn: 181597
2013-05-10 22:09:52 +08:00
; PR15948
define <4 x i32> @test10(<4 x i32> %a) nounwind {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test10:
; X32: # %bb.0:
; X32-NEXT: andnps {{\.LCPI.*}}, %xmm0
; X32-NEXT: retl
;
; X64-LIN-LABEL: test10:
; X64-LIN: # %bb.0:
; X64-LIN-NEXT: andnps {{.*}}(%rip), %xmm0
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test10:
; X64-WIN: # %bb.0:
; X64-WIN-NEXT: movaps (%rcx), %xmm0
; X64-WIN-NEXT: andnps __xmm@{{.*}}(%rip), %xmm0
; X64-WIN-NEXT: retq
DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)). PR15948. llvm-svn: 181597
2013-05-10 22:09:52 +08:00
%1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
%2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
ret <4 x i32> %2
}
DAGCombiner: Don't fold xor into not if getNOT would introduce an illegal constant. This happens e.g. with <2 x i64> -1 on x86_32. It cannot be generated directly because i64 is illegal. It would be nice if getNOT would handle this transparently, but I don't see a way to generate a legal constant there right now. Fixes PR17487. llvm-svn: 192795
2013-10-16 22:16:19 +08:00
define i32 @PR17487(i1 %tobool) {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: PR17487:
; X32: # %bb.0:
; X32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; X32-NEXT: pandn {{\.LCPI.*}}, %xmm0
; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
; X32-NEXT: movd %xmm1, %ecx
; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X32-NEXT: movd %xmm0, %edx
; X32-NEXT: xorl $1, %edx
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: orl %ecx, %edx
; X32-NEXT: setne %al
; X32-NEXT: retl
;
; X64-LIN-LABEL: PR17487:
; X64-LIN: # %bb.0:
; X64-LIN-NEXT: movd %edi, %xmm0
; X64-LIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; X64-LIN-NEXT: pandn {{.*}}(%rip), %xmm0
; X64-LIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X64-LIN-NEXT: movq %xmm0, %rcx
; X64-LIN-NEXT: xorl %eax, %eax
; X64-LIN-NEXT: cmpq $1, %rcx
; X64-LIN-NEXT: setne %al
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: PR17487:
; X64-WIN: # %bb.0:
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32 Summary: Re-lands r328386 and r328443, reverting r328482. Incorporates fixes from @mstorsjo in D44876 (thanks!) so that small parameters in i8 and i16 do not end up in the SysV register parameters (EDI, ESI, etc). I added tests for how we receive small parameters, since that is the important part. It's always safe to store more bytes than will be read, but the assumptions you make when loading them are what really matter. I also tested this by self-hosting clang and it passed tests on win64. Reviewers: mstorsjo, hans Subscribers: hiraditya, mstorsjo, llvm-commits Differential Revision: https://reviews.llvm.org/D44900 llvm-svn: 328570
2018-03-27 02:49:48 +08:00
; X64-WIN-NEXT: movzbl %cl, %eax
; X64-WIN-NEXT: movd %eax, %xmm0
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-WIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; X64-WIN-NEXT: pandn __xmm@{{.*}}(%rip), %xmm0
; X64-WIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X64-WIN-NEXT: movq %xmm0, %rcx
; X64-WIN-NEXT: xorl %eax, %eax
; X64-WIN-NEXT: cmpq $1, %rcx
; X64-WIN-NEXT: setne %al
; X64-WIN-NEXT: retq
DAGCombiner: Don't fold xor into not if getNOT would introduce an illegal constant. This happens e.g. with <2 x i64> -1 on x86_32. It cannot be generated directly because i64 is illegal. It would be nice if getNOT would handle this transparently, but I don't see a way to generate a legal constant there right now. Fixes PR17487. llvm-svn: 192795
2013-10-16 22:16:19 +08:00
%tmp = insertelement <2 x i1> undef, i1 %tobool, i32 1
%tmp1 = zext <2 x i1> %tmp to <2 x i64>
%tmp2 = xor <2 x i64> %tmp1, <i64 1, i64 1>
%tmp3 = extractelement <2 x i64> %tmp2, i32 1
%add = add nsw i64 0, %tmp3
%cmp6 = icmp ne i64 %add, 1
%conv7 = zext i1 %cmp6 to i32
ret i32 %conv7
}
DAGCombiner: fold (xor (shl 1, x), -1) -> (rotl ~1, x) Targets which provide a rotate make it possible to replace a sequence of (XOR (SHL 1, x), -1) with (ROTL ~1, x). This saves an instruction on architectures like X86 and POWER(64). Differential Revision: http://reviews.llvm.org/D8350 llvm-svn: 232572
2015-03-18 08:03:36 +08:00
define i32 @test11(i32 %b) {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test11:
; X32: # %bb.0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movl $-2, %eax
; X32-NEXT: roll %cl, %eax
; X32-NEXT: retl
;
; X64-LIN-LABEL: test11:
; X64-LIN: # %bb.0:
; X64-LIN-NEXT: movl %edi, %ecx
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-LIN-NEXT: movl $-2, %eax
; X64-LIN-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X64-LIN-NEXT: roll %cl, %eax
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test11:
; X64-WIN: # %bb.0:
; X64-WIN-NEXT: movl $-2, %eax
; X64-WIN-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-WIN-NEXT: roll %cl, %eax
; X64-WIN-NEXT: retq
DAGCombiner: fold (xor (shl 1, x), -1) -> (rotl ~1, x) Targets which provide a rotate make it possible to replace a sequence of (XOR (SHL 1, x), -1) with (ROTL ~1, x). This saves an instruction on architectures like X86 and POWER(64). Differential Revision: http://reviews.llvm.org/D8350 llvm-svn: 232572
2015-03-18 08:03:36 +08:00
%shl = shl i32 1, %b
%neg = xor i32 %shl, -1
ret i32 %neg
}
[DAGCombine] Fix demanded bits computation for exact shifts. Fixes a miscompilation of MultiSource/Benchmarks/MallocBench/gs llvm-svn: 240796
2015-06-27 00:59:31 +08:00
%struct.ref_s = type { %union.v, i16, i16 }
%union.v = type { i64 }
define %struct.ref_s* @test12(%struct.ref_s* %op, i64 %osbot, i64 %intval) {
[X86] Regenerate XOR tests llvm-svn: 325579
2018-02-20 22:08:39 +08:00
; X32-LABEL: test12:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: notl %eax
; X32-NEXT: leal (%eax,%eax,2), %eax
; X32-NEXT: shll $2, %eax
; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
;
; X64-LIN-LABEL: test12:
; X64-LIN: # %bb.0:
; X64-LIN-NEXT: xorq $-1, %rdx
; X64-LIN-NEXT: shlq $32, %rdx
; X64-LIN-NEXT: sarq $28, %rdx
; X64-LIN-NEXT: leaq (%rdx,%rdi), %rax
; X64-LIN-NEXT: retq
;
; X64-WIN-LABEL: test12:
; X64-WIN: # %bb.0:
; X64-WIN-NEXT: xorq $-1, %r8
; X64-WIN-NEXT: shlq $32, %r8
; X64-WIN-NEXT: sarq $28, %r8
; X64-WIN-NEXT: leaq (%r8,%rcx), %rax
; X64-WIN-NEXT: retq
[DAGCombine] Fix demanded bits computation for exact shifts. Fixes a miscompilation of MultiSource/Benchmarks/MallocBench/gs llvm-svn: 240796
2015-06-27 00:59:31 +08:00
%neg = shl i64 %intval, 32
%sext = xor i64 %neg, -4294967296
%idx.ext = ashr exact i64 %sext, 32
%add.ptr = getelementptr inbounds %struct.ref_s, %struct.ref_s* %op, i64 %idx.ext
ret %struct.ref_s* %add.ptr
}