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llvm-project/llvm/test/CodeGen/X86/stack-folding-tbm.ll

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[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+bmi,+tbm < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown"
; Stack reload folding tests.
;
; By including a nop call with sideeffects we can force a partial register spill of the
; relevant registers and check that the reload is correctly folded into the instruction.
define i32 @stack_fold_bextri_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_bextri_u32
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
;CHECK: # %bb.0:
[X86][TBM] Use realistic BEXTR control bits Avoid constant values that are guaranteed to give zero Found while investigating BEXTR optimizations for PR34042. llvm-svn: 333849
2018-06-04 02:15:06 +08:00
;CHECK: bextrl $3841, {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
[X86][TBM] Use realistic BEXTR control bits Avoid constant values that are guaranteed to give zero Found while investigating BEXTR optimizations for PR34042. llvm-svn: 333849
2018-06-04 02:15:06 +08:00
%2 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a0, i32 3841)
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
ret i32 %2
}
declare i32 @llvm.x86.tbm.bextri.u32(i32, i32)
define i64 @stack_fold_bextri_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_bextri_u64
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
;CHECK: # %bb.0:
[X86][TBM] Use realistic BEXTR control bits Avoid constant values that are guaranteed to give zero Found while investigating BEXTR optimizations for PR34042. llvm-svn: 333849
2018-06-04 02:15:06 +08:00
;CHECK: bextrq $3841, {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
[X86][TBM] Use realistic BEXTR control bits Avoid constant values that are guaranteed to give zero Found while investigating BEXTR optimizations for PR34042. llvm-svn: 333849
2018-06-04 02:15:06 +08:00
%2 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a0, i64 3841)
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
ret i64 %2
}
declare i64 @llvm.x86.tbm.bextri.u64(i64, i64)
define i32 @stack_fold_blcfill_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcfill_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcfilll {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = and i32 %a0, %2
ret i32 %3
}
define i64 @stack_fold_blcfill_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcfill_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcfillq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = and i64 %a0, %2
ret i64 %3
}
define i32 @stack_fold_blci_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blci_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcil {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %2, -1
%4 = or i32 %a0, %3
ret i32 %4
}
define i64 @stack_fold_blci_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blci_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blciq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %2, -1
%4 = or i64 %a0, %3
ret i64 %4
}
define i32 @stack_fold_blcic_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcic_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcicl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %a0, -1
%4 = and i32 %2, %3
ret i32 %4
}
define i64 @stack_fold_blcic_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcic_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcicq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %a0, -1
%4 = and i64 %2, %3
ret i64 %4
}
define i32 @stack_fold_blcmsk_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcmsk_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcmskl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %a0, %2
ret i32 %3
}
define i64 @stack_fold_blcmsk_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcmsk_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcmskq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %a0, %2
ret i64 %3
}
define i32 @stack_fold_blcs_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blcs_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcsl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = or i32 %a0, %2
ret i32 %3
}
define i64 @stack_fold_blcs_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blcs_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blcsq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = or i64 %a0, %2
ret i64 %3
}
define i32 @stack_fold_blsfill_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blsfill_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blsfilll {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i32 %a0, 1
%3 = or i32 %a0, %2
ret i32 %3
}
define i64 @stack_fold_blsfill_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blsfill_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blsfillq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i64 %a0, 1
%3 = or i64 %a0, %2
ret i64 %3
}
define i32 @stack_fold_blsic_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_blsic_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blsicl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i32 %a0, 1
%3 = xor i32 %a0, -1
%4 = or i32 %2, %3
ret i32 %4
}
define i64 @stack_fold_blsic_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_blsic_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: blsicq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i64 %a0, 1
%3 = xor i64 %a0, -1
%4 = or i64 %2, %3
ret i64 %4
}
define i32 @stack_fold_t1mskc_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_t1mskc_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: t1mskcl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i32 %a0, 1
%3 = xor i32 %a0, -1
%4 = or i32 %2, %3
ret i32 %4
}
define i64 @stack_fold_t1mskc_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_t1mskc_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: t1mskcq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = add i64 %a0, 1
%3 = xor i64 %a0, -1
%4 = or i64 %2, %3
ret i64 %4
}
define i32 @stack_fold_tzmsk_u32(i32 %a0) {
;CHECK-LABEL: stack_fold_tzmsk_u32
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: tzmskl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i32 %a0, 1
%3 = xor i32 %a0, -1
%4 = and i32 %2, %3
ret i32 %4
}
define i64 @stack_fold_tzmsk_u64(i64 %a0) {
;CHECK-LABEL: stack_fold_tzmsk_u64
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
2018-01-12 14:21:36 +08:00
;CHECK: tzmskq {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 8-byte Folded Reload
[X86][TBM] Add TBM stack folding tests llvm-svn: 295477
2017-02-18 02:51:53 +08:00
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%2 = sub i64 %a0, 1
%3 = xor i64 %a0, -1
%4 = and i64 %2, %3
ret i64 %4
}