2017-11-21 17:30:33 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+vpclmulqdq | FileCheck %s
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; FIXME: actual vpclmulqdq operation should be eliminated
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declare <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64>, <4 x i64>, i8) nounwind readnone
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define <4 x i64> @commute_v1(<4 x i64> %a0, <4 x i64> %a1) {
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; CHECK-LABEL: commute_v1:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2017-11-21 17:30:33 +08:00
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; CHECK-NEXT: vpclmulqdq $0, %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a0, <4 x i64> %a1, i8 0)
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%2 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a1, <4 x i64> %a0, i8 0)
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%3 = xor <4 x i64> %1, %2
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_v2(<4 x i64> %a0, <4 x i64> %a1) {
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; CHECK-LABEL: commute_v2:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2017-11-21 17:30:33 +08:00
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; CHECK-NEXT: vpclmulqdq $16, %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a0, <4 x i64> %a1, i8 16)
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%2 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a1, <4 x i64> %a0, i8 1)
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%3 = xor <4 x i64> %2, %1
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ret <4 x i64> %3
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}
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define <4 x i64> @commute_v3(<4 x i64> %a0, <4 x i64> %a1) {
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; CHECK-LABEL: commute_v3:
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2017-12-05 01:18:51 +08:00
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; CHECK: # %bb.0:
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2017-11-21 17:30:33 +08:00
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; CHECK-NEXT: vpclmulqdq $17, %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a0, <4 x i64> %a1, i8 17)
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%2 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a1, <4 x i64> %a0, i8 17)
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%3 = xor <4 x i64> %2, %1
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ret <4 x i64> %3
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}
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