maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/clwb-schedule.ll

19 lines
715 B
LLVM
Raw Normal View History

[X86] Add CLWB schedule test llvm-svn: 320644
2017-12-14 06:09:09 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+clwb | FileCheck %s --check-prefix=GENERIC
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx | FileCheck %s --check-prefix=SKX
define void @clwb(i8* %a0) nounwind {
; GENERIC-LABEL: clwb:
; GENERIC: # %bb.0:
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; GENERIC-NEXT: clwb (%rdi) # sched: [5:0.50]
[X86] Add CLWB schedule test llvm-svn: 320644
2017-12-14 06:09:09 +08:00
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: clwb:
; SKX: # %bb.0:
; SKX-NEXT: clwb (%rdi) # sched: [5:0.50]
; SKX-NEXT: retq # sched: [7:1.00]
tail call void @llvm.x86.clwb(i8* %a0)
ret void
}
declare void @llvm.x86.clwb(i8*) nounwind