maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/bmi.ll

684 lines
18 KiB
LLVM
Raw Normal View History

VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR Summary: This function turns (X >> C1) & C2 into a BMI BEXTR or TBM BEXTRI instruction. For BMI BEXTR we have to materialize an immediate into a register to feed to the BEXTR instruction. The BMI BEXTR instruction is 2 uops on Intel CPUs. It looks like on SKL its one port 0/6 uop and one port 1/5 uop. Despite what Agner's tables say. I know one of the uops is a regular shift uop so it would have to go through the port 0/6 shifter unit. So that's the same or worse execution wise than the shift+and which is one 0/6 uop and one 0/1/5/6 uop. The move immediate into register is an additional 0/1/5/6 uop. For now I've limited this transform to AMD CPUs which have a single uop BEXTR. If may also might make sense if we can fold a load or if the and immediate is larger than 32-bits and can't be encoded as a sign extended 32-bit value or if LICM or CSE can hoist the move immediate and share it. But we'd need to look more carefully at that. In the regression I looked at it doesn't look load folding or large immediates were occurring so the regression isn't caused by the loss of those. So we could try to be smarter here if we find a compelling case. Reviewers: RKSimon, spatel, lebedev.ri, andreadb Reviewed By: RKSimon Subscribers: llvm-commits, andreadb, RKSimon Differential Revision: https://reviews.llvm.org/D52570 llvm-svn: 343399
2018-09-30 11:01:46 +08:00
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefixes=CHECK,X86,X86-SLOW-BEXTR
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK,X86,X86-SLOW-BEXTR
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefixes=CHECK,X64,X64-SLOW-BEXTR
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK,X64,X64-SLOW-BEXTR
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi,+fast-bextr | FileCheck %s --check-prefixes=CHECK,X86,X86-FAST-BEXTR
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+fast-bextr | FileCheck %s --check-prefixes=CHECK,X64,X64-FAST-BEXTR
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @andn32(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: andn32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: retl
;
; X64-LABEL: andn32:
; X64: # %bb.0:
; X64-NEXT: andnl %esi, %edi, %eax
; X64-NEXT: retq
Add X86 ANDN instruction. Including instruction selection. llvm-svn: 141947
2011-10-14 15:06:56 +08:00
%tmp1 = xor i32 %x, -1
%tmp2 = and i32 %y, %tmp1
ret i32 %tmp2
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @andn32_load(i32 %x, i32* %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: andn32_load:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andnl (%eax), %ecx, %eax
; X86-NEXT: retl
;
; X64-LABEL: andn32_load:
; X64: # %bb.0:
; X64-NEXT: andnl (%rsi), %edi, %eax
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%y1 = load i32, i32* %y
Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt. llvm-svn: 170304
2012-12-17 13:02:29 +08:00
%tmp1 = xor i32 %x, -1
%tmp2 = and i32 %y1, %tmp1
ret i32 %tmp2
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i64 @andn64(i64 %x, i64 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: andn64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: andnl {{[0-9]+}}(%esp), %ecx, %edx
; X86-NEXT: retl
;
; X64-LABEL: andn64:
; X64: # %bb.0:
; X64-NEXT: andnq %rsi, %rdi, %rax
; X64-NEXT: retq
Add X86 ANDN instruction. Including instruction selection. llvm-svn: 141947
2011-10-14 15:06:56 +08:00
%tmp1 = xor i64 %x, -1
%tmp2 = and i64 %tmp1, %y
ret i64 %tmp2
}
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
[x86] use BMI 'andn' for logic + compare ops With BMI, we can use 'andn' to save an instruction when the result is only used in a compare. This is related to one of the potential sequences to check 'isfinite' in: https://llvm.org/bugs/show_bug.cgi?id=27164 Differential Revision: http://reviews.llvm.org/D18910 llvm-svn: 265875
2016-04-10 00:02:52 +08:00
; Don't choose a 'test' if an 'andn' can be used.
[x86] show missed opportunities to use andn llvm-svn: 265850
2016-04-09 05:26:11 +08:00
define i1 @andn_cmp(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: andn_cmp:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: sete %al
; X86-NEXT: retl
;
; X64-LABEL: andn_cmp:
; X64: # %bb.0:
; X64-NEXT: andnl %esi, %edi, %eax
; X64-NEXT: sete %al
; X64-NEXT: retq
[x86] show missed opportunities to use andn llvm-svn: 265850
2016-04-09 05:26:11 +08:00
%notx = xor i32 %x, -1
%and = and i32 %notx, %y
%cmp = icmp eq i32 %and, 0
ret i1 %cmp
}
[x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
2016-05-07 23:03:40 +08:00
; Recognize a disguised andn in the following 4 tests.
[x86] add tests to show potential BMI optimization llvm-svn: 266243
2016-04-14 04:40:43 +08:00
define i1 @and_cmp1(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: and_cmp1:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: sete %al
; X86-NEXT: retl
;
; X64-LABEL: and_cmp1:
; X64: # %bb.0:
; X64-NEXT: andnl %esi, %edi, %eax
; X64-NEXT: sete %al
; X64-NEXT: retq
[x86] add tests to show potential BMI optimization llvm-svn: 266243
2016-04-14 04:40:43 +08:00
%and = and i32 %x, %y
%cmp = icmp eq i32 %and, %y
ret i1 %cmp
}
define i1 @and_cmp2(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: and_cmp2:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: setne %al
; X86-NEXT: retl
;
; X64-LABEL: and_cmp2:
; X64: # %bb.0:
; X64-NEXT: andnl %esi, %edi, %eax
; X64-NEXT: setne %al
; X64-NEXT: retq
[x86] add tests to show potential BMI optimization llvm-svn: 266243
2016-04-14 04:40:43 +08:00
%and = and i32 %y, %x
%cmp = icmp ne i32 %and, %y
ret i1 %cmp
}
define i1 @and_cmp3(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: and_cmp3:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: sete %al
; X86-NEXT: retl
;
; X64-LABEL: and_cmp3:
; X64: # %bb.0:
; X64-NEXT: andnl %esi, %edi, %eax
; X64-NEXT: sete %al
; X64-NEXT: retq
[x86] add tests to show potential BMI optimization llvm-svn: 266243
2016-04-14 04:40:43 +08:00
%and = and i32 %x, %y
%cmp = icmp eq i32 %y, %and
ret i1 %cmp
}
define i1 @and_cmp4(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: and_cmp4:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: setne %al
; X86-NEXT: retl
;
; X64-LABEL: and_cmp4:
; X64: # %bb.0:
; X64-NEXT: andnl %esi, %edi, %eax
; X64-NEXT: setne %al
; X64-NEXT: retq
[x86] add tests to show potential BMI optimization llvm-svn: 266243
2016-04-14 04:40:43 +08:00
%and = and i32 %y, %x
%cmp = icmp ne i32 %y, %and
ret i1 %cmp
}
; A mask and compare against constant is ok for an 'andn' too
; even though the BMI instruction doesn't have an immediate form.
define i1 @and_cmp_const(i32 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: and_cmp_const:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: notl %eax
; X86-NEXT: andl $43, %eax
; X86-NEXT: sete %al
; X86-NEXT: retl
;
; X64-LABEL: and_cmp_const:
; X64: # %bb.0:
; X64-NEXT: notl %edi
; X64-NEXT: andl $43, %edi
; X64-NEXT: sete %al
; X64-NEXT: retq
[x86] add tests to show potential BMI optimization llvm-svn: 266243
2016-04-14 04:40:43 +08:00
%and = and i32 %x, 43
%cmp = icmp eq i32 %and, 43
ret i1 %cmp
}
[x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
2016-05-07 23:03:40 +08:00
; But don't use 'andn' if the mask is a power-of-two.
define i1 @and_cmp_const_power_of_two(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: and_cmp_const_power_of_two:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: btl %ecx, %eax
; X86-NEXT: setae %al
; X86-NEXT: retl
;
; X64-LABEL: and_cmp_const_power_of_two:
; X64: # %bb.0:
; X64-NEXT: btl %esi, %edi
; X64-NEXT: setae %al
; X64-NEXT: retq
[x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
2016-05-07 23:03:40 +08:00
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp ne i32 %and, %shl
ret i1 %cmp
}
; Don't transform to 'andn' if there's another use of the 'and'.
define i32 @and_cmp_not_one_use(i32 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: and_cmp_not_one_use:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andl $37, %ecx
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: cmpl $37, %ecx
; X86-NEXT: sete %al
; X86-NEXT: addl %ecx, %eax
; X86-NEXT: retl
;
; X64-LABEL: and_cmp_not_one_use:
; X64: # %bb.0:
; X64-NEXT: andl $37, %edi
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: cmpl $37, %edi
; X64-NEXT: sete %al
; X64-NEXT: addl %edi, %eax
; X64-NEXT: retq
[x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
2016-05-07 23:03:40 +08:00
%and = and i32 %x, 37
%cmp = icmp eq i32 %and, 37
%ext = zext i1 %cmp to i32
%add = add i32 %and, %ext
ret i32 %add
}
; Verify that we're not transforming invalid comparison predicates.
define i1 @not_an_andn1(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: not_an_andn1:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andl %eax, %ecx
; X86-NEXT: cmpl %ecx, %eax
; X86-NEXT: setg %al
; X86-NEXT: retl
;
; X64-LABEL: not_an_andn1:
; X64: # %bb.0:
; X64-NEXT: andl %esi, %edi
; X64-NEXT: cmpl %edi, %esi
; X64-NEXT: setg %al
; X64-NEXT: retq
[x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
2016-05-07 23:03:40 +08:00
%and = and i32 %x, %y
%cmp = icmp sgt i32 %y, %and
ret i1 %cmp
}
define i1 @not_an_andn2(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: not_an_andn2:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andl %eax, %ecx
; X86-NEXT: cmpl %ecx, %eax
; X86-NEXT: setbe %al
; X86-NEXT: retl
;
; X64-LABEL: not_an_andn2:
; X64: # %bb.0:
; X64-NEXT: andl %esi, %edi
; X64-NEXT: cmpl %edi, %esi
; X64-NEXT: setbe %al
; X64-NEXT: retq
[x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
2016-05-07 23:03:40 +08:00
%and = and i32 %y, %x
%cmp = icmp ule i32 %y, %and
ret i1 %cmp
}
[x86] use BMI 'andn' for logic + compare ops With BMI, we can use 'andn' to save an instruction when the result is only used in a compare. This is related to one of the potential sequences to check 'isfinite' in: https://llvm.org/bugs/show_bug.cgi?id=27164 Differential Revision: http://reviews.llvm.org/D18910 llvm-svn: 265875
2016-04-10 00:02:52 +08:00
; Don't choose a 'test' if an 'andn' can be used.
[x86] show missed opportunities to use andn llvm-svn: 265850
2016-04-09 05:26:11 +08:00
define i1 @andn_cmp_swap_ops(i64 %x, i64 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: andn_cmp_swap_ops:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: andnl {{[0-9]+}}(%esp), %ecx, %ecx
; X86-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax
; X86-NEXT: orl %ecx, %eax
; X86-NEXT: sete %al
; X86-NEXT: retl
;
; X64-LABEL: andn_cmp_swap_ops:
; X64: # %bb.0:
; X64-NEXT: andnq %rsi, %rdi, %rax
; X64-NEXT: sete %al
; X64-NEXT: retq
[x86] show missed opportunities to use andn llvm-svn: 265850
2016-04-09 05:26:11 +08:00
%notx = xor i64 %x, -1
%and = and i64 %y, %notx
%cmp = icmp eq i64 %and, 0
ret i1 %cmp
}
; Use a 'test' (not an 'and') because 'andn' only works for i32/i64.
define i1 @andn_cmp_i8(i8 %x, i8 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: andn_cmp_i8:
; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: notb %al
; X86-NEXT: testb %al, {{[0-9]+}}(%esp)
; X86-NEXT: sete %al
; X86-NEXT: retl
;
; X64-LABEL: andn_cmp_i8:
; X64: # %bb.0:
; X64-NEXT: notb %sil
; X64-NEXT: testb %sil, %dil
; X64-NEXT: sete %al
; X64-NEXT: retq
[x86] show missed opportunities to use andn llvm-svn: 265850
2016-04-09 05:26:11 +08:00
%noty = xor i8 %y, -1
%and = and i8 %x, %noty
%cmp = icmp eq i8 %and, 0
ret i1 %cmp
}
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
declare i32 @llvm.x86.bmi.bextr.32(i32, i32)
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @bextr32(i32 %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: bextr32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: bextr32:
; X64: # %bb.0:
; X64-NEXT: bextrl %esi, %edi, %eax
; X64-NEXT: retq
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
ret i32 %tmp
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @bextr32_load(i32* %x, i32 %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: bextr32_load:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: bextrl %eax, (%ecx), %eax
; X86-NEXT: retl
;
; X64-LABEL: bextr32_load:
; X64: # %bb.0:
; X64-NEXT: bextrl %esi, (%rdi), %eax
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x1 = load i32, i32* %x
Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt. llvm-svn: 170304
2012-12-17 13:02:29 +08:00
%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y)
ret i32 %tmp
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @bextr32b(i32 %x) uwtable ssp {
[X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR Summary: This function turns (X >> C1) & C2 into a BMI BEXTR or TBM BEXTRI instruction. For BMI BEXTR we have to materialize an immediate into a register to feed to the BEXTR instruction. The BMI BEXTR instruction is 2 uops on Intel CPUs. It looks like on SKL its one port 0/6 uop and one port 1/5 uop. Despite what Agner's tables say. I know one of the uops is a regular shift uop so it would have to go through the port 0/6 shifter unit. So that's the same or worse execution wise than the shift+and which is one 0/6 uop and one 0/1/5/6 uop. The move immediate into register is an additional 0/1/5/6 uop. For now I've limited this transform to AMD CPUs which have a single uop BEXTR. If may also might make sense if we can fold a load or if the and immediate is larger than 32-bits and can't be encoded as a sign extended 32-bit value or if LICM or CSE can hoist the move immediate and share it. But we'd need to look more carefully at that. In the regression I looked at it doesn't look load folding or large immediates were occurring so the regression isn't caused by the loss of those. So we could try to be smarter here if we find a compelling case. Reviewers: RKSimon, spatel, lebedev.ri, andreadb Reviewed By: RKSimon Subscribers: llvm-commits, andreadb, RKSimon Differential Revision: https://reviews.llvm.org/D52570 llvm-svn: 343399
2018-09-30 11:01:46 +08:00
; X86-SLOW-BEXTR-LABEL: bextr32b:
; X86-SLOW-BEXTR: # %bb.0:
; X86-SLOW-BEXTR-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SLOW-BEXTR-NEXT: shrl $4, %eax
; X86-SLOW-BEXTR-NEXT: andl $4095, %eax # imm = 0xFFF
; X86-SLOW-BEXTR-NEXT: retl
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
;
[X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR Summary: This function turns (X >> C1) & C2 into a BMI BEXTR or TBM BEXTRI instruction. For BMI BEXTR we have to materialize an immediate into a register to feed to the BEXTR instruction. The BMI BEXTR instruction is 2 uops on Intel CPUs. It looks like on SKL its one port 0/6 uop and one port 1/5 uop. Despite what Agner's tables say. I know one of the uops is a regular shift uop so it would have to go through the port 0/6 shifter unit. So that's the same or worse execution wise than the shift+and which is one 0/6 uop and one 0/1/5/6 uop. The move immediate into register is an additional 0/1/5/6 uop. For now I've limited this transform to AMD CPUs which have a single uop BEXTR. If may also might make sense if we can fold a load or if the and immediate is larger than 32-bits and can't be encoded as a sign extended 32-bit value or if LICM or CSE can hoist the move immediate and share it. But we'd need to look more carefully at that. In the regression I looked at it doesn't look load folding or large immediates were occurring so the regression isn't caused by the loss of those. So we could try to be smarter here if we find a compelling case. Reviewers: RKSimon, spatel, lebedev.ri, andreadb Reviewed By: RKSimon Subscribers: llvm-commits, andreadb, RKSimon Differential Revision: https://reviews.llvm.org/D52570 llvm-svn: 343399
2018-09-30 11:01:46 +08:00
; X64-SLOW-BEXTR-LABEL: bextr32b:
; X64-SLOW-BEXTR: # %bb.0:
; X64-SLOW-BEXTR-NEXT: movl %edi, %eax
; X64-SLOW-BEXTR-NEXT: shrl $4, %eax
; X64-SLOW-BEXTR-NEXT: andl $4095, %eax # imm = 0xFFF
; X64-SLOW-BEXTR-NEXT: retq
;
; X86-FAST-BEXTR-LABEL: bextr32b:
; X86-FAST-BEXTR: # %bb.0:
; X86-FAST-BEXTR-NEXT: movl $3076, %eax # imm = 0xC04
; X86-FAST-BEXTR-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-FAST-BEXTR-NEXT: retl
;
; X64-FAST-BEXTR-LABEL: bextr32b:
; X64-FAST-BEXTR: # %bb.0:
; X64-FAST-BEXTR-NEXT: movl $3076, %eax # imm = 0xC04
; X64-FAST-BEXTR-NEXT: bextrl %eax, %edi, %eax
; X64-FAST-BEXTR-NEXT: retq
Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028. llvm-svn: 189742
2013-09-02 15:53:17 +08:00
%1 = lshr i32 %x, 4
%2 = and i32 %1, 4095
ret i32 %2
}
[X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel Recognizing this pattern during DAG combine hides information about the 'and' and the shift from other combines. I think it should be recognized at isel so its as late as possible. But it can't be done with table based isel because you need to be able to look at both immediates. This patch moves it to custom isel in X86ISelDAGToDAG.cpp. This does break a couple tests in tbm_patterns because we are now emitting an and_flag node or (cmp and, 0) that we dont' recognize yet. We already had this problem for several other TBM patterns so I think this fine and we can address of them together. I've also fixed a bug where the combine to BEXTR was preventing us from using a trick of zero extending AH to handle extracts of bits 15:8. We might still want to use BEXTR if it enables load folding. But honestly I hope we narrowed the load instead before got to isel. I think we should probably also support matching BEXTR from (srl/srl (and mask << C), C). But that should be a different patch. Differential Revision: https://reviews.llvm.org/D37592 llvm-svn: 313054
2017-09-13 01:40:25 +08:00
; Make sure we still use AH subreg trick to extract 15:8
define i32 @bextr32_subreg(i32 %x) uwtable ssp {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: bextr32_subreg:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: bextr32_subreg:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: movzbl %ah, %eax
; X64-NEXT: retq
[X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel Recognizing this pattern during DAG combine hides information about the 'and' and the shift from other combines. I think it should be recognized at isel so its as late as possible. But it can't be done with table based isel because you need to be able to look at both immediates. This patch moves it to custom isel in X86ISelDAGToDAG.cpp. This does break a couple tests in tbm_patterns because we are now emitting an and_flag node or (cmp and, 0) that we dont' recognize yet. We already had this problem for several other TBM patterns so I think this fine and we can address of them together. I've also fixed a bug where the combine to BEXTR was preventing us from using a trick of zero extending AH to handle extracts of bits 15:8. We might still want to use BEXTR if it enables load folding. But honestly I hope we narrowed the load instead before got to isel. I think we should probably also support matching BEXTR from (srl/srl (and mask << C), C). But that should be a different patch. Differential Revision: https://reviews.llvm.org/D37592 llvm-svn: 313054
2017-09-13 01:40:25 +08:00
%1 = lshr i32 %x, 8
%2 = and i32 %1, 255
ret i32 %2
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @bextr32b_load(i32* %x) uwtable ssp {
[X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR Summary: This function turns (X >> C1) & C2 into a BMI BEXTR or TBM BEXTRI instruction. For BMI BEXTR we have to materialize an immediate into a register to feed to the BEXTR instruction. The BMI BEXTR instruction is 2 uops on Intel CPUs. It looks like on SKL its one port 0/6 uop and one port 1/5 uop. Despite what Agner's tables say. I know one of the uops is a regular shift uop so it would have to go through the port 0/6 shifter unit. So that's the same or worse execution wise than the shift+and which is one 0/6 uop and one 0/1/5/6 uop. The move immediate into register is an additional 0/1/5/6 uop. For now I've limited this transform to AMD CPUs which have a single uop BEXTR. If may also might make sense if we can fold a load or if the and immediate is larger than 32-bits and can't be encoded as a sign extended 32-bit value or if LICM or CSE can hoist the move immediate and share it. But we'd need to look more carefully at that. In the regression I looked at it doesn't look load folding or large immediates were occurring so the regression isn't caused by the loss of those. So we could try to be smarter here if we find a compelling case. Reviewers: RKSimon, spatel, lebedev.ri, andreadb Reviewed By: RKSimon Subscribers: llvm-commits, andreadb, RKSimon Differential Revision: https://reviews.llvm.org/D52570 llvm-svn: 343399
2018-09-30 11:01:46 +08:00
; X86-SLOW-BEXTR-LABEL: bextr32b_load:
; X86-SLOW-BEXTR: # %bb.0:
; X86-SLOW-BEXTR-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SLOW-BEXTR-NEXT: movl (%eax), %eax
; X86-SLOW-BEXTR-NEXT: shrl $4, %eax
; X86-SLOW-BEXTR-NEXT: andl $4095, %eax # imm = 0xFFF
; X86-SLOW-BEXTR-NEXT: retl
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
;
[X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR Summary: This function turns (X >> C1) & C2 into a BMI BEXTR or TBM BEXTRI instruction. For BMI BEXTR we have to materialize an immediate into a register to feed to the BEXTR instruction. The BMI BEXTR instruction is 2 uops on Intel CPUs. It looks like on SKL its one port 0/6 uop and one port 1/5 uop. Despite what Agner's tables say. I know one of the uops is a regular shift uop so it would have to go through the port 0/6 shifter unit. So that's the same or worse execution wise than the shift+and which is one 0/6 uop and one 0/1/5/6 uop. The move immediate into register is an additional 0/1/5/6 uop. For now I've limited this transform to AMD CPUs which have a single uop BEXTR. If may also might make sense if we can fold a load or if the and immediate is larger than 32-bits and can't be encoded as a sign extended 32-bit value or if LICM or CSE can hoist the move immediate and share it. But we'd need to look more carefully at that. In the regression I looked at it doesn't look load folding or large immediates were occurring so the regression isn't caused by the loss of those. So we could try to be smarter here if we find a compelling case. Reviewers: RKSimon, spatel, lebedev.ri, andreadb Reviewed By: RKSimon Subscribers: llvm-commits, andreadb, RKSimon Differential Revision: https://reviews.llvm.org/D52570 llvm-svn: 343399
2018-09-30 11:01:46 +08:00
; X64-SLOW-BEXTR-LABEL: bextr32b_load:
; X64-SLOW-BEXTR: # %bb.0:
; X64-SLOW-BEXTR-NEXT: movl (%rdi), %eax
; X64-SLOW-BEXTR-NEXT: shrl $4, %eax
; X64-SLOW-BEXTR-NEXT: andl $4095, %eax # imm = 0xFFF
; X64-SLOW-BEXTR-NEXT: retq
;
; X86-FAST-BEXTR-LABEL: bextr32b_load:
; X86-FAST-BEXTR: # %bb.0:
; X86-FAST-BEXTR-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-FAST-BEXTR-NEXT: movl $3076, %ecx # imm = 0xC04
; X86-FAST-BEXTR-NEXT: bextrl %ecx, (%eax), %eax
; X86-FAST-BEXTR-NEXT: retl
;
; X64-FAST-BEXTR-LABEL: bextr32b_load:
; X64-FAST-BEXTR: # %bb.0:
; X64-FAST-BEXTR-NEXT: movl $3076, %eax # imm = 0xC04
; X64-FAST-BEXTR-NEXT: bextrl %eax, (%rdi), %eax
; X64-FAST-BEXTR-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%1 = load i32, i32* %x
Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028. llvm-svn: 189742
2013-09-02 15:53:17 +08:00
%2 = lshr i32 %1, 4
%3 = and i32 %2, 4095
ret i32 %3
}
[X86][BMI] Add BEXTR demanded bits test cases (PR34042) llvm-svn: 310802
2017-08-14 04:35:38 +08:00
; PR34042
define i32 @bextr32c(i32 %x, i16 zeroext %y) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: bextr32c:
; X86: # %bb.0:
; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: bextr32c:
; X64: # %bb.0:
[X86][BMI][TBM] Only demand bottom 16-bits of the BEXTR control op (PR34042) Only the bottom 16-bits of BEXTR's control op are required (0:8 INDEX, 15:8 LENGTH). Differential Revision: https://reviews.llvm.org/D47690 llvm-svn: 334083
2018-06-06 18:52:10 +08:00
; X64-NEXT: bextrl %esi, %edi, %eax
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X64-NEXT: retq
[X86][BMI] Add BEXTR demanded bits test cases (PR34042) llvm-svn: 310802
2017-08-14 04:35:38 +08:00
%tmp0 = sext i16 %y to i32
%tmp1 = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %tmp0)
ret i32 %tmp1
}
Add testcases for BEXTR. These BEXTR cases are a check for the 64-bit load form and two negative cases where the bitrange is non-contiguous. From a private patch equivalent to r189742/PR17028. llvm-svn: 232580
2015-03-18 09:34:06 +08:00
define i32 @non_bextr32(i32 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: non_bextr32:
; X86: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $2, %eax
; X86-NEXT: andl $111, %eax
; X86-NEXT: retl
;
; X64-LABEL: non_bextr32:
; X64: # %bb.0: # %entry
; X64-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: shrl $2, %eax
; X64-NEXT: andl $111, %eax
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X64-NEXT: retq
Add testcases for BEXTR. These BEXTR cases are a check for the 64-bit load form and two negative cases where the bitrange is non-contiguous. From a private patch equivalent to r189742/PR17028. llvm-svn: 232580
2015-03-18 09:34:06 +08:00
entry:
%shr = lshr i32 %x, 2
%and = and i32 %shr, 111
ret i32 %and
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @blsi32(i32 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsi32:
; X86: # %bb.0:
; X86-NEXT: blsil {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: blsi32:
; X64: # %bb.0:
; X64-NEXT: blsil %edi, %eax
; X64-NEXT: retq
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
2011-10-21 14:55:01 +08:00
%tmp = sub i32 0, %x
%tmp2 = and i32 %x, %tmp
ret i32 %tmp2
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @blsi32_load(i32* %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsi32_load:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: blsil (%eax), %eax
; X86-NEXT: retl
;
; X64-LABEL: blsi32_load:
; X64: # %bb.0:
; X64-NEXT: blsil (%rdi), %eax
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x1 = load i32, i32* %x
Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt. llvm-svn: 170304
2012-12-17 13:02:29 +08:00
%tmp = sub i32 0, %x1
%tmp2 = and i32 %x1, %tmp
ret i32 %tmp2
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i64 @blsi64(i64 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsi64:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: negl %eax
; X86-NEXT: sbbl %esi, %edx
; X86-NEXT: andl %esi, %edx
; X86-NEXT: andl %ecx, %eax
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
; X64-LABEL: blsi64:
; X64: # %bb.0:
; X64-NEXT: blsiq %rdi, %rax
; X64-NEXT: retq
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
2011-10-21 14:55:01 +08:00
%tmp = sub i64 0, %x
%tmp2 = and i64 %tmp, %x
ret i64 %tmp2
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @blsmsk32(i32 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsmsk32:
; X86: # %bb.0:
; X86-NEXT: blsmskl {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: blsmsk32:
; X64: # %bb.0:
; X64-NEXT: blsmskl %edi, %eax
; X64-NEXT: retq
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
2011-10-21 14:55:01 +08:00
%tmp = sub i32 %x, 1
%tmp2 = xor i32 %x, %tmp
ret i32 %tmp2
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @blsmsk32_load(i32* %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsmsk32_load:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: blsmskl (%eax), %eax
; X86-NEXT: retl
;
; X64-LABEL: blsmsk32_load:
; X64: # %bb.0:
; X64-NEXT: blsmskl (%rdi), %eax
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x1 = load i32, i32* %x
Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt. llvm-svn: 170304
2012-12-17 13:02:29 +08:00
%tmp = sub i32 %x1, 1
%tmp2 = xor i32 %x1, %tmp
ret i32 %tmp2
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i64 @blsmsk64(i64 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsmsk64:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: addl $-1, %eax
; X86-NEXT: movl %esi, %edx
; X86-NEXT: adcl $-1, %edx
; X86-NEXT: xorl %ecx, %eax
; X86-NEXT: xorl %esi, %edx
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
; X64-LABEL: blsmsk64:
; X64: # %bb.0:
; X64-NEXT: blsmskq %rdi, %rax
; X64-NEXT: retq
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
2011-10-21 14:55:01 +08:00
%tmp = sub i64 %x, 1
%tmp2 = xor i64 %tmp, %x
ret i64 %tmp2
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @blsr32(i32 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsr32:
; X86: # %bb.0:
; X86-NEXT: blsrl {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: blsr32:
; X64: # %bb.0:
; X64-NEXT: blsrl %edi, %eax
; X64-NEXT: retq
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
2011-10-21 14:55:01 +08:00
%tmp = sub i32 %x, 1
%tmp2 = and i32 %x, %tmp
ret i32 %tmp2
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i32 @blsr32_load(i32* %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsr32_load:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: blsrl (%eax), %eax
; X86-NEXT: retl
;
; X64-LABEL: blsr32_load:
; X64: # %bb.0:
; X64-NEXT: blsrl (%rdi), %eax
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%x1 = load i32, i32* %x
Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt. llvm-svn: 170304
2012-12-17 13:02:29 +08:00
%tmp = sub i32 %x1, 1
%tmp2 = and i32 %x1, %tmp
ret i32 %tmp2
}
[x86] regenerate checks for BMI tests llvm-svn: 265841
2016-04-09 04:29:39 +08:00
define i64 @blsr64(i64 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsr64:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: addl $-1, %eax
; X86-NEXT: movl %esi, %edx
; X86-NEXT: adcl $-1, %edx
; X86-NEXT: andl %ecx, %eax
; X86-NEXT: andl %esi, %edx
; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
; X64-LABEL: blsr64:
; X64: # %bb.0:
; X64-NEXT: blsrq %rdi, %rax
; X64-NEXT: retq
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. llvm-svn: 142642
2011-10-21 14:55:01 +08:00
%tmp = sub i64 %x, 1
%tmp2 = and i64 %tmp, %x
ret i64 %tmp2
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. llvm-svn: 142480
2011-10-19 15:48:35 +08:00
}
[x86] add test to show missed BMI isel; NFC llvm-svn: 324403
2018-02-07 05:18:53 +08:00
; PR35792 - https://bugs.llvm.org/show_bug.cgi?id=35792
define i64 @blsr_disguised_constant(i64 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsr_disguised_constant:
; X86: # %bb.0:
; X86-NEXT: blsrl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
; X64-LABEL: blsr_disguised_constant:
; X64: # %bb.0:
; X64-NEXT: blsrl %edi, %eax
; X64-NEXT: movzwl %ax, %eax
; X64-NEXT: retq
[x86] add test to show missed BMI isel; NFC llvm-svn: 324403
2018-02-07 05:18:53 +08:00
%a1 = and i64 %x, 65535
%a2 = add i64 %x, 65535
%r = and i64 %a1, %a2
ret i64 %r
}
[X86] Add combine to shrink 64-bit ands when one input is an any_extend and the other input guarantees upper 32 bits are 0. Summary: This gets the shift case from PR35792. Reviewers: spatel, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43222 llvm-svn: 325018
2018-02-14 00:25:25 +08:00
; The add here used to get shrunk, but the and did not thus hiding the blsr pattern.
; We now use the knowledge that upper bits of the shift guarantee the and result has 0s in the upper bits to reduce it too.
[X86] Add a blsr test case with a shift from PR35792. NFC The blsr pattern here is missed because the add is shrunk, but the and is not. This leaves an any_extend between them. llvm-svn: 324986
2018-02-13 13:33:39 +08:00
define i64 @blsr_disguised_shrunk_add(i64 %x) {
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests Further refactoring will wait until D47452 has landed. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333841
2018-06-03 22:11:34 +08:00
; X86-LABEL: blsr_disguised_shrunk_add:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $16, %eax
; X86-NEXT: blsrl %eax, %eax
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
; X64-LABEL: blsr_disguised_shrunk_add:
; X64: # %bb.0:
; X64-NEXT: shrq $48, %rdi
; X64-NEXT: blsrl %edi, %eax
; X64-NEXT: retq
[X86] Add a blsr test case with a shift from PR35792. NFC The blsr pattern here is missed because the add is shrunk, but the and is not. This leaves an any_extend between them. llvm-svn: 324986
2018-02-13 13:33:39 +08:00
%a = lshr i64 %x, 48
%b = add i64 %a, -1
%c = and i64 %b, %a
ret i64 %c
}