[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.
The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
LLVM :: CodeGen/X86/GlobalISel/gep.ll
LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
-; X64-NEXT: movsbl %dil, %eax
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: shll %cl, %edi
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: sarl %cl, %edi
+; X64-NEXT: movl %edi, %eax
..which is not optimal and should be addressed later.
Rework of the patch by igorb
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44395
llvm-svn: 327499
2018-03-14 19:23:57 +08:00
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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2018-05-06 05:19:59 +08:00
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.
The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
LLVM :: CodeGen/X86/GlobalISel/gep.ll
LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
-; X64-NEXT: movsbl %dil, %eax
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: shll %cl, %edi
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: sarl %cl, %edi
+; X64-NEXT: movl %edi, %eax
..which is not optimal and should be addressed later.
Rework of the patch by igorb
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44395
llvm-svn: 327499
2018-03-14 19:23:57 +08:00
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--- |
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define i64 @test_ashr_i64(i64 %arg1, i64 %arg2) {
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%res = ashr i64 %arg1, %arg2
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ret i64 %res
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}
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define i64 @test_ashr_i64_imm(i64 %arg1) {
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%res = ashr i64 %arg1, 5
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ret i64 %res
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}
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define i64 @test_ashr_i64_imm1(i64 %arg1) {
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%res = ashr i64 %arg1, 1
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ret i64 %res
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}
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define i32 @test_ashr_i32(i32 %arg1, i32 %arg2) {
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%res = ashr i32 %arg1, %arg2
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ret i32 %res
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}
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define i32 @test_ashr_i32_imm(i32 %arg1) {
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%res = ashr i32 %arg1, 5
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ret i32 %res
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}
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define i32 @test_ashr_i32_imm1(i32 %arg1) {
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%res = ashr i32 %arg1, 1
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ret i32 %res
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}
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define i16 @test_ashr_i16(i32 %arg1, i32 %arg2) {
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%a = trunc i32 %arg1 to i16
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%a2 = trunc i32 %arg2 to i16
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%res = ashr i16 %a, %a2
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ret i16 %res
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}
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define i16 @test_ashr_i16_imm(i32 %arg1) {
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%a = trunc i32 %arg1 to i16
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%res = ashr i16 %a, 5
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ret i16 %res
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}
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define i16 @test_ashr_i16_imm1(i32 %arg1) {
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%a = trunc i32 %arg1 to i16
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%res = ashr i16 %a, 1
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ret i16 %res
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}
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define i8 @test_ashr_i8(i32 %arg1, i32 %arg2) {
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%a = trunc i32 %arg1 to i8
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%a2 = trunc i32 %arg2 to i8
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%res = ashr i8 %a, %a2
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ret i8 %res
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}
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define i8 @test_ashr_i8_imm(i32 %arg1) {
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%a = trunc i32 %arg1 to i8
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%res = ashr i8 %a, 5
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ret i8 %res
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}
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define i8 @test_ashr_i8_imm1(i32 %arg1) {
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%a = trunc i32 %arg1 to i8
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%res = ashr i8 %a, 1
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ret i8 %res
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}
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...
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---
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name: test_ashr_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; ALL-LABEL: name: test_ashr_i64
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; ALL: liveins: $rdi, $rsi
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; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
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; ALL: $rcx = COPY [[COPY1]]
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; ALL: $cl = KILL killed $rcx
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; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl
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; ALL: $rax = COPY [[SAR64rCL]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_ASHR %0, %1
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: test_ashr_i64_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi
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; ALL-LABEL: name: test_ashr_i64_imm
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; ALL: liveins: $rdi
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; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 5
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; ALL: $rcx = COPY [[MOV64ri32_]]
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; ALL: $cl = KILL killed $rcx
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; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl
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; ALL: $rax = COPY [[SAR64rCL]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s64) = G_CONSTANT i64 5
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%2(s64) = G_ASHR %0, %1
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: test_ashr_i64_imm1
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi
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; ALL-LABEL: name: test_ashr_i64_imm1
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; ALL: liveins: $rdi
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; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 1
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; ALL: $rcx = COPY [[MOV64ri32_]]
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; ALL: $cl = KILL killed $rcx
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; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl
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; ALL: $rax = COPY [[SAR64rCL]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s64) = G_CONSTANT i64 1
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%2(s64) = G_ASHR %0, %1
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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|
---
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|
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name: test_ashr_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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|
constants:
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|
body: |
|
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; ALL-LABEL: name: test_ashr_i32
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; ALL: liveins: $edi, $esi
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; ALL: $ecx = COPY [[COPY1]]
|
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|
; ALL: $cl = KILL killed $ecx
|
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|
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; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl
|
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|
; ALL: $eax = COPY [[SAR32rCL]]
|
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; ALL: RET 0, implicit $eax
|
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|
%0(s32) = COPY $edi
|
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|
|
%1(s32) = COPY $esi
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|
|
%2(s32) = G_ASHR %0, %1
|
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|
$eax = COPY %2(s32)
|
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RET 0, implicit $eax
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|
|
|
|
|
|
|
...
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|
|
|
---
|
|
|
|
name: test_ashr_i32_imm
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alignment: 4
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legalized: true
|
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regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
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|
- { id: 0, class: gpr, preferred-register: '' }
|
|
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|
- { id: 1, class: gpr, preferred-register: '' }
|
|
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- { id: 2, class: gpr, preferred-register: '' }
|
|
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|
liveins:
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fixedStack:
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|
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stack:
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|
|
|
constants:
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|
|
|
body: |
|
|
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|
bb.1 (%ir-block.0):
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liveins: $edi
|
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|
|
|
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; ALL-LABEL: name: test_ashr_i32_imm
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; ALL: liveins: $edi
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 5
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; ALL: $ecx = COPY [[MOV32ri]]
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; ALL: $cl = KILL killed $ecx
|
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; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl
|
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|
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; ALL: $eax = COPY [[SAR32rCL]]
|
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; ALL: RET 0, implicit $eax
|
|
|
|
%0(s32) = COPY $edi
|
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|
|
%1(s32) = G_CONSTANT i32 5
|
|
|
|
%2(s32) = G_ASHR %0, %1
|
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|
$eax = COPY %2(s32)
|
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|
RET 0, implicit $eax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_ashr_i32_imm1
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alignment: 4
|
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|
legalized: true
|
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|
regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
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|
- { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
|
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liveins:
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|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: $edi
|
|
|
|
|
|
|
|
; ALL-LABEL: name: test_ashr_i32_imm1
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; ALL: liveins: $edi
|
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
|
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; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
|
|
|
|
; ALL: $ecx = COPY [[MOV32ri]]
|
|
|
|
; ALL: $cl = KILL killed $ecx
|
|
|
|
; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl
|
|
|
|
; ALL: $eax = COPY [[SAR32rCL]]
|
|
|
|
; ALL: RET 0, implicit $eax
|
|
|
|
%0(s32) = COPY $edi
|
|
|
|
%1(s32) = G_CONSTANT i32 1
|
|
|
|
%2(s32) = G_ASHR %0, %1
|
|
|
|
$eax = COPY %2(s32)
|
|
|
|
RET 0, implicit $eax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_ashr_i16
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 4, class: gpr, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: $edi, $esi
|
|
|
|
|
|
|
|
; ALL-LABEL: name: test_ashr_i16
|
|
|
|
; ALL: liveins: $edi, $esi
|
|
|
|
; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
|
|
; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
|
|
|
|
; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
|
|
|
|
; ALL: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
|
|
|
|
; ALL: $cx = COPY [[COPY3]]
|
|
|
|
; ALL: $cl = KILL killed $cx
|
|
|
|
; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY2]], implicit-def $eflags, implicit $cl
|
|
|
|
; ALL: $ax = COPY [[SAR16rCL]]
|
|
|
|
; ALL: RET 0, implicit $ax
|
|
|
|
%0(s32) = COPY $edi
|
|
|
|
%1(s32) = COPY $esi
|
|
|
|
%2(s16) = G_TRUNC %0(s32)
|
|
|
|
%3(s16) = G_TRUNC %1(s32)
|
|
|
|
%4(s16) = G_ASHR %2, %3
|
|
|
|
$ax = COPY %4(s16)
|
|
|
|
RET 0, implicit $ax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_ashr_i16_imm
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: $edi
|
|
|
|
|
|
|
|
; ALL-LABEL: name: test_ashr_i16_imm
|
|
|
|
; ALL: liveins: $edi
|
|
|
|
; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
|
|
; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 5
|
|
|
|
; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
|
|
|
|
; ALL: $cx = COPY [[MOV16ri]]
|
|
|
|
; ALL: $cl = KILL killed $cx
|
|
|
|
; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY1]], implicit-def $eflags, implicit $cl
|
|
|
|
; ALL: $ax = COPY [[SAR16rCL]]
|
|
|
|
; ALL: RET 0, implicit $ax
|
|
|
|
%0(s32) = COPY $edi
|
|
|
|
%2(s16) = G_CONSTANT i16 5
|
|
|
|
%1(s16) = G_TRUNC %0(s32)
|
|
|
|
%3(s16) = G_ASHR %1, %2
|
|
|
|
$ax = COPY %3(s16)
|
|
|
|
RET 0, implicit $ax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_ashr_i16_imm1
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: $edi
|
|
|
|
|
|
|
|
; ALL-LABEL: name: test_ashr_i16_imm1
|
|
|
|
; ALL: liveins: $edi
|
|
|
|
; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
|
|
; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 1
|
|
|
|
; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
|
|
|
|
; ALL: $cx = COPY [[MOV16ri]]
|
|
|
|
; ALL: $cl = KILL killed $cx
|
|
|
|
; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY1]], implicit-def $eflags, implicit $cl
|
|
|
|
; ALL: $ax = COPY [[SAR16rCL]]
|
|
|
|
; ALL: RET 0, implicit $ax
|
|
|
|
%0(s32) = COPY $edi
|
|
|
|
%2(s16) = G_CONSTANT i16 1
|
|
|
|
%1(s16) = G_TRUNC %0(s32)
|
|
|
|
%3(s16) = G_ASHR %1, %2
|
|
|
|
$ax = COPY %3(s16)
|
|
|
|
RET 0, implicit $ax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_ashr_i8
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 4, class: gpr, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: $edi, $esi
|
|
|
|
|
|
|
|
; ALL-LABEL: name: test_ashr_i8
|
|
|
|
; ALL: liveins: $edi, $esi
|
|
|
|
; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
|
|
; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
|
|
|
|
; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
|
|
|
|
; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
|
|
|
|
; ALL: $cl = COPY [[COPY3]]
|
|
|
|
; ALL: [[SAR8rCL:%[0-9]+]]:gr8 = SAR8rCL [[COPY2]], implicit-def $eflags, implicit $cl
|
|
|
|
; ALL: $al = COPY [[SAR8rCL]]
|
|
|
|
; ALL: RET 0, implicit $al
|
|
|
|
%0(s32) = COPY $edi
|
|
|
|
%1(s32) = COPY $esi
|
|
|
|
%2(s8) = G_TRUNC %0(s32)
|
|
|
|
%3(s8) = G_TRUNC %1(s32)
|
|
|
|
%4(s8) = G_ASHR %2, %3
|
|
|
|
$al = COPY %4(s8)
|
|
|
|
RET 0, implicit $al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_ashr_i8_imm
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: $edi
|
|
|
|
|
|
|
|
; ALL-LABEL: name: test_ashr_i8_imm
|
|
|
|
; ALL: liveins: $edi
|
|
|
|
; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
|
|
; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
|
|
|
|
; ALL: [[SAR8ri:%[0-9]+]]:gr8 = SAR8ri [[COPY1]], 5, implicit-def $eflags
|
|
|
|
; ALL: $al = COPY [[SAR8ri]]
|
|
|
|
; ALL: RET 0, implicit $al
|
|
|
|
%0(s32) = COPY $edi
|
|
|
|
%2(s8) = G_CONSTANT i8 5
|
|
|
|
%1(s8) = G_TRUNC %0(s32)
|
|
|
|
%3(s8) = G_ASHR %1, %2
|
|
|
|
$al = COPY %3(s8)
|
|
|
|
RET 0, implicit $al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_ashr_i8_imm1
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
tracksRegLiveness: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: $edi
|
|
|
|
|
|
|
|
; ALL-LABEL: name: test_ashr_i8_imm1
|
|
|
|
; ALL: liveins: $edi
|
|
|
|
; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
|
|
; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
|
|
|
|
; ALL: [[SAR8r1_:%[0-9]+]]:gr8 = SAR8r1 [[COPY1]], implicit-def $eflags
|
|
|
|
; ALL: $al = COPY [[SAR8r1_]]
|
|
|
|
; ALL: RET 0, implicit $al
|
|
|
|
%0(s32) = COPY $edi
|
|
|
|
%2(s8) = G_CONSTANT i8 1
|
|
|
|
%1(s8) = G_TRUNC %0(s32)
|
|
|
|
%3(s8) = G_ASHR %1, %2
|
|
|
|
$al = COPY %3(s8)
|
|
|
|
RET 0, implicit $al
|
|
|
|
|
|
|
|
...
|