[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.
The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
LLVM :: CodeGen/X86/GlobalISel/gep.ll
LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
-; X64-NEXT: movsbl %dil, %eax
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: shll %cl, %edi
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: sarl %cl, %edi
+; X64-NEXT: movl %edi, %eax
..which is not optimal and should be addressed later.
Rework of the patch by igorb
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44395
llvm-svn: 327499
2018-03-14 19:23:57 +08:00
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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2018-05-06 05:19:59 +08:00
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
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[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.
The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
LLVM :: CodeGen/X86/GlobalISel/gep.ll
LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
-; X64-NEXT: movsbl %dil, %eax
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: shll %cl, %edi
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: sarl %cl, %edi
+; X64-NEXT: movl %edi, %eax
..which is not optimal and should be addressed later.
Rework of the patch by igorb
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44395
llvm-svn: 327499
2018-03-14 19:23:57 +08:00
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--- |
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define void @test_ashr() { ret void }
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define void @test_ashr_i1() { ret void }
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...
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---
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name: test_ashr
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alignment: 4
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legalized: false
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regBankSelected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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- { id: 5, class: _, preferred-register: '' }
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- { id: 6, class: _, preferred-register: '' }
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- { id: 7, class: _, preferred-register: '' }
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- { id: 8, class: _, preferred-register: '' }
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- { id: 9, class: _, preferred-register: '' }
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- { id: 10, class: _, preferred-register: '' }
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- { id: 11, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_ashr
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; CHECK: liveins: $rdi, $rsi
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
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; CHECK: RET 0
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_ASHR %0, %1
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%3(s32) = G_TRUNC %0
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%4(s32) = G_TRUNC %1
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%5(s32) = G_ASHR %3, %4
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%6(s16) = G_TRUNC %0
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%7(s16) = G_TRUNC %1
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%8(s16) = G_ASHR %6, %7
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%9(s8) = G_TRUNC %0
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%10(s8) = G_TRUNC %1
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%11(s8) = G_ASHR %9, %10
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RET 0
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...
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---
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name: test_ashr_i1
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alignment: 4
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legalized: false
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regBankSelected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_ashr_i1
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; CHECK: liveins: $rdi, $rsi
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
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; CHECK: RET 0
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s1) = G_TRUNC %0
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%3(s1) = G_TRUNC %1
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%4(s1) = G_ASHR %2, %3
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RET 0
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...
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