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llvm-project/llvm/test/CodeGen/Hexagon/early-if-debug.mir

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[Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-if llvm-svn: 310524
2017-08-10 05:22:05 +08:00
# RUN: llc -march=hexagon -eif-limit=4 -run-pass hexagon-early-if -o - %s | FileCheck %s
# Check that even with the limit of 4 instructions, the block bb.1 is
# if-converted.
# CHECK-LABEL: bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: %0:intregs = COPY $r0
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
# CHECK: %1:predregs = C2_cmpeqi %0, 0
# CHECK: %2:intregs = A2_tfrsi 123
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
# CHECK: %3:intregs = A2_tfrsi 321
# CHECK: %5:intregs = C2_mux %1, %2, %3
[Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-if llvm-svn: 310524
2017-08-10 05:22:05 +08:00
--- |
define void @foo() {
ret void
}
!1 = !DIExpression()
...
---
name: foo
tracksRegLiveness: true
registers:
- { id: 0, class: intregs }
- { id: 1, class: predregs }
- { id: 2, class: intregs }
- { id: 3, class: intregs }
- { id: 4, class: intregs }
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0
[Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-if llvm-svn: 310524
2017-08-10 05:22:05 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
%0 = COPY $r0
[Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-if llvm-svn: 310524
2017-08-10 05:22:05 +08:00
%1 = C2_cmpeqi %0, 0
%2 = A2_tfrsi 123
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
J2_jumpt %1, %bb.2, implicit-def dead $pc
J2_jump %bb.1, implicit-def dead $pc
[Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-if llvm-svn: 310524
2017-08-10 05:22:05 +08:00
bb.1:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
[Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-if llvm-svn: 310524
2017-08-10 05:22:05 +08:00
%3 = A2_tfrsi 321
bb.2:
%4 = PHI %2, %bb.0, %3, %bb.1
...