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llvm-project/llvm/test/CodeGen/AArch64/tbz-tbnz.ll

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[AArch64] Prefer Bcc to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free". This patch contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions into a conditional branch (Bcc), when the NZCV flags can be set for "free". This is preferred on targets that have more flexibility when scheduling Bcc instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming all other variables are equal). This can reduce register pressure and is also the default behavior for GCC. A few examples: add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS. cbz w8, .LBB_2 -> b.eq .LBB0_2 ; single def/use of w8 removed. add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses. cbz w8, .LBB1_2 -> b.eq .LBB1_2 sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses. tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2 In looking at all current sub-target machine descriptions, this transformation appears to be either positive or neutral. Differential Revision: https://reviews.llvm.org/D34220. llvm-svn: 306144
2017-06-24 03:20:12 +08:00
; RUN: llc < %s -O1 -mtriple=aarch64-eabi -aarch64-enable-cond-br-tune=false | FileCheck %s
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
declare void @t()
define void @test1(i32 %a) {
; CHECK-LABEL: @test1
entry:
%sub = add nsw i32 %a, -12
%cmp = icmp slt i32 %sub, 0
br i1 %cmp, label %if.then, label %if.end
; CHECK: sub [[CMP:w[0-9]+]], w0, #12
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz [[CMP]], #31
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test2(i64 %a) {
; CHECK-LABEL: @test2
entry:
%sub = add nsw i64 %a, -12
%cmp = icmp slt i64 %sub, 0
br i1 %cmp, label %if.then, label %if.end
; CHECK: sub [[CMP:x[0-9]+]], x0, #12
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz [[CMP]], #63
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test3(i32 %a) {
; CHECK-LABEL: @test3
entry:
%sub = add nsw i32 %a, -12
%cmp = icmp sgt i32 %sub, -1
br i1 %cmp, label %if.then, label %if.end
; CHECK: sub [[CMP:w[0-9]+]], w0, #12
; CHECK: tbnz [[CMP]], #31
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test4(i64 %a) {
; CHECK-LABEL: @test4
entry:
%sub = add nsw i64 %a, -12
%cmp = icmp sgt i64 %sub, -1
br i1 %cmp, label %if.then, label %if.end
; CHECK: sub [[CMP:x[0-9]+]], x0, #12
; CHECK: tbnz [[CMP]], #63
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test5(i32 %a) {
; CHECK-LABEL: @test5
entry:
%sub = add nsw i32 %a, -12
%cmp = icmp sge i32 %sub, 0
br i1 %cmp, label %if.then, label %if.end
; CHECK: sub [[CMP:w[0-9]+]], w0, #12
; CHECK: tbnz [[CMP]], #31
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test6(i64 %a) {
; CHECK-LABEL: @test6
entry:
%sub = add nsw i64 %a, -12
%cmp = icmp sge i64 %sub, 0
br i1 %cmp, label %if.then, label %if.end
; CHECK: sub [[CMP:x[0-9]+]], x0, #12
; CHECK: tbnz [[CMP]], #63
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test7(i32 %a) {
; CHECK-LABEL: @test7
entry:
%sub = sub nsw i32 %a, 12
%cmp = icmp slt i32 %sub, 0
br i1 %cmp, label %if.then, label %if.end
; CHECK: sub [[CMP:w[0-9]+]], w0, #12
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz [[CMP]], #31
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test8(i64 %val1, i64 %val2, i64 %val3) {
; CHECK-LABEL: @test8
%and1 = and i64 %val1, %val2
%tst1 = icmp slt i64 %and1, 0
br i1 %tst1, label %if.then1, label %if.end
; CHECK: tst x0, x1
[AArch64] Fix test from r214518 in an attempt to appease buildbots. llvm-svn: 214521
2014-08-01 23:30:41 +08:00
; CHECK-NEXT: b.ge
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then1:
%and2 = and i64 %val2, %val3
%tst2 = icmp sge i64 %and2, 0
br i1 %tst2, label %if.then2, label %if.end
; CHECK: and [[CMP:x[0-9]+]], x1, x2
; CHECK-NOT: cmp
[AArch64] Fix test from r214518 in an attempt to appease buildbots. llvm-svn: 214521
2014-08-01 23:30:41 +08:00
; CHECK: tbnz [[CMP]], #63
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then2:
%shifted_op1 = shl i64 %val2, 63
%shifted_and1 = and i64 %val1, %shifted_op1
%tst3 = icmp slt i64 %shifted_and1, 0
br i1 %tst3, label %if.then3, label %if.end
; CHECK: tst x0, x1, lsl #63
[AArch64] Fix test from r214518 in an attempt to appease buildbots. llvm-svn: 214521
2014-08-01 23:30:41 +08:00
; CHECK: b.ge
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then3:
%shifted_op2 = shl i64 %val2, 62
%shifted_and2 = and i64 %val1, %shifted_op2
%tst4 = icmp sge i64 %shifted_and2, 0
br i1 %tst4, label %if.then4, label %if.end
; CHECK: tst x0, x1, lsl #62
[AArch64] Fix test from r214518 in an attempt to appease buildbots. llvm-svn: 214521
2014-08-01 23:30:41 +08:00
; CHECK: b.lt
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then4:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test9(i64 %val1) {
; CHECK-LABEL: @test9
%tst = icmp slt i64 %val1, 0
br i1 %tst, label %if.then, label %if.end
; CHECK-NOT: cmp
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz x0, #63
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test10(i64 %val1) {
; CHECK-LABEL: @test10
%tst = icmp slt i64 %val1, 0
br i1 %tst, label %if.then, label %if.end
; CHECK-NOT: cmp
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz x0, #63
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test11(i64 %val1, i64* %ptr) {
; CHECK-LABEL: @test11
; CHECK: ldr [[CMP:x[0-9]+]], [x1]
; CHECK-NOT: cmp
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz [[CMP]], #63
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%val = load i64, i64* %ptr
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
%tst = icmp slt i64 %val, 0
br i1 %tst, label %if.then, label %if.end
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test12(i64 %val1) {
; CHECK-LABEL: @test12
%tst = icmp slt i64 %val1, 0
br i1 %tst, label %if.then, label %if.end
; CHECK-NOT: cmp
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz x0, #63
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test13(i64 %val1, i64 %val2) {
; CHECK-LABEL: @test13
%or = or i64 %val1, %val2
%tst = icmp slt i64 %or, 0
br i1 %tst, label %if.then, label %if.end
; CHECK: orr [[CMP:x[0-9]+]], x0, x1
; CHECK-NOT: cmp
CodeGen: Allow small copyable blocks to "break" the CFG. When choosing the best successor for a block, ordinarily we would have preferred a block that preserves the CFG unless there is a strong probability the other direction. For small blocks that can be duplicated we now skip that requirement as well, subject to some simple frequency calculations. Differential Revision: https://reviews.llvm.org/D28583 llvm-svn: 293716
2017-02-01 07:48:32 +08:00
; CHECK: tbnz [[CMP]], #63
[AArch64] Generate tbz/tbnz when comparing against zero. The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
2014-08-01 22:48:56 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
[AArch64] Optimize some simple TBZ/TBNZ cases. Summary: Add some AArch64 dag combines to optimize some simple TBZ/TBNZ cases: (tbz (and x, m), b) -> (tbz x, b) (tbz (shl x, c), b) -> (tbz x, b-c) (tbz (shr x, c), b) -> (tbz x, b+c) (tbz (xor x, -1), b) -> (tbnz x, b) Reviewers: jmolloy, mcrosier, t.p.northover Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D15702 llvm-svn: 256765
2016-01-05 02:55:47 +08:00
define void @test14(i1 %cond) {
; CHECK-LABEL: @test14
br i1 %cond, label %if.end, label %if.then
; CHECK-NOT: and
Revert "CodeGen: Allow small copyable blocks to "break" the CFG." This reverts commit ada6595a526d71df04988eb0a4b4fe84df398ded. This needs a simple probability check because there are some cases where it is not profitable. llvm-svn: 291695
2017-01-12 03:55:19 +08:00
; CHECK: tbnz w0, #0
[AArch64] Optimize some simple TBZ/TBNZ cases. Summary: Add some AArch64 dag combines to optimize some simple TBZ/TBNZ cases: (tbz (and x, m), b) -> (tbz x, b) (tbz (shl x, c), b) -> (tbz x, b-c) (tbz (shr x, c), b) -> (tbz x, b+c) (tbz (xor x, -1), b) -> (tbnz x, b) Reviewers: jmolloy, mcrosier, t.p.northover Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D15702 llvm-svn: 256765
2016-01-05 02:55:47 +08:00
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test15(i1 %cond) {
; CHECK-LABEL: @test15
%cond1 = xor i1 %cond, -1
br i1 %cond1, label %if.then, label %if.end
; CHECK-NOT: movn
; CHECK: tbnz w0, #0
if.then:
call void @t()
br label %if.end
if.end:
ret void
}
define void @test16(i64 %in) {
; CHECK-LABEL: @test16
%shl = shl i64 %in, 3
%and = and i64 %shl, 32
%cond = icmp eq i64 %and, 0
br i1 %cond, label %then, label %end
; CHECK-NOT: lsl
; CHECK: tbnz w0, #2
then:
call void @t()
br label %end
end:
ret void
}
define void @test17(i64 %in) {
; CHECK-LABEL: @test17
%shr = ashr i64 %in, 3
%and = and i64 %shr, 1
%cond = icmp eq i64 %and, 0
br i1 %cond, label %then, label %end
; CHECK-NOT: lsr
; CHECK: tbnz w0, #3
then:
call void @t()
br label %end
end:
ret void
}
define void @test18(i32 %in) {
; CHECK-LABEL: @test18
%shr = ashr i32 %in, 2
%cond = icmp sge i32 %shr, 0
br i1 %cond, label %then, label %end
; CHECK-NOT: asr
; CHECK: tbnz w0, #31
then:
call void @t()
br label %end
end:
ret void
}
define void @test19(i64 %in) {
; CHECK-LABEL: @test19
%shl = lshr i64 %in, 3
%trunc = trunc i64 %shl to i32
%and = and i32 %trunc, 1
%cond = icmp eq i32 %and, 0
br i1 %cond, label %then, label %end
; CHECK-NOT: ubfx
; CHECK: tbnz w0, #3
then:
call void @t()
br label %end
end:
ret void
}