2016-07-19 21:35:11 +08:00
|
|
|
; RUN: llc < %s -mtriple=arm64-eabi -mcpu=generic -aarch64-neon-syntax=apple | FileCheck %s
|
2014-04-18 04:51:50 +08:00
|
|
|
|
|
|
|
define void @test0f(float* nocapture %x, float %a) #0 {
|
|
|
|
entry:
|
|
|
|
%0 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %a, i32 0
|
|
|
|
%1 = bitcast float* %x to <4 x float>*
|
|
|
|
store <4 x float> %0, <4 x float>* %1, align 16
|
|
|
|
ret void
|
|
|
|
|
|
|
|
; CHECK-LABEL: test0f
|
[AArch64] Improve code generation of constant vectors
Use the whole gammut of constant immediates available to set up a vector.
Instead of using, for example, `mov w0, #0xffff; dup v0.4s, w0`, which
transfers between register files, use the more efficient `movi v0.4s, #-1`
instead. Not limited to just a few values, but any immediate value that can
be encoded by all the variants of `FMOV`, `MOVI`, `MVNI`, thus eliminating
the need to there be patterns to optimize special cases.
Differential revision: https://reviews.llvm.org/D42133
llvm-svn: 326718
2018-03-06 01:02:47 +08:00
|
|
|
; CHECK: movi.2d v[[TEMP:[0-9]+]], #0
|
[AArch64][TableGen] Skip tied result operands for InstAlias
Summary:
This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias.
This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests.
Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch.
Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka
Reviewed By: rengolin, SjoerdMeijer
Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D40030
llvm-svn: 318650
2017-11-20 22:36:40 +08:00
|
|
|
; CHECK: mov.s v[[TEMP]][0], v{{[0-9]+}}[0]
|
2014-04-18 04:51:50 +08:00
|
|
|
; CHECK: str q[[TEMP]], [x0]
|
|
|
|
; CHECK: ret
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test1f(float* nocapture %x, float %a) #0 {
|
|
|
|
entry:
|
|
|
|
%0 = insertelement <4 x float> <float undef, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, float %a, i32 0
|
|
|
|
%1 = bitcast float* %x to <4 x float>*
|
|
|
|
store <4 x float> %0, <4 x float>* %1, align 16
|
|
|
|
ret void
|
|
|
|
|
|
|
|
; CHECK-LABEL: test1f
|
[AArch64] Improve code generation of constant vectors
Use the whole gammut of constant immediates available to set up a vector.
Instead of using, for example, `mov w0, #0xffff; dup v0.4s, w0`, which
transfers between register files, use the more efficient `movi v0.4s, #-1`
instead. Not limited to just a few values, but any immediate value that can
be encoded by all the variants of `FMOV`, `MOVI`, `MVNI`, thus eliminating
the need to there be patterns to optimize special cases.
Differential revision: https://reviews.llvm.org/D42133
llvm-svn: 326718
2018-03-06 01:02:47 +08:00
|
|
|
; CHECK: fmov.4s v[[TEMP:[0-9]+]], #1.0
|
|
|
|
; CHECK: mov.s v[[TEMP]][0], v0[0]
|
|
|
|
; CHECK: str q[[TEMP]], [x0]
|
2014-04-18 04:51:50 +08:00
|
|
|
; CHECK: ret
|
|
|
|
}
|