2012-08-01 05:49:49 +08:00
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//===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
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2012-08-01 05:49:49 +08:00
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#include "MipsInstrInfo.h"
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2012-08-01 07:41:32 +08:00
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#include "MipsSERegisterInfo.h"
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2012-08-01 05:49:49 +08:00
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namespace llvm {
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class MipsSEInstrInfo : public MipsInstrInfo {
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const MipsSERegisterInfo RI;
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public:
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explicit MipsSEInstrInfo(const MipsSubtarget &STI);
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const MipsRegisterInfo &getRegisterInfo() const override;
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const override;
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void loadRegFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const override;
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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unsigned getOppositeBranchOpc(unsigned Opc) const override;
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/// Adjust SP by Amount bytes.
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void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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/// Emit a series of instructions to load an immediate. If NewImm is a
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/// non-NULL parameter, the last instruction is not emitted, but instead
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/// its immediate operand is returned in NewImm.
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unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned *NewImm) const;
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private:
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unsigned getAnalyzableBrOpc(unsigned Opc) const override;
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2012-08-01 05:49:49 +08:00
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[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
llvm-svn: 212604
2014-07-09 18:16:07 +08:00
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void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
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2013-05-17 03:57:23 +08:00
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2013-06-12 02:48:16 +08:00
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std::pair<bool, bool> compareOpndSize(unsigned Opc,
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const MachineFunction &MF) const;
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2013-06-08 08:14:54 +08:00
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2013-10-08 02:49:46 +08:00
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void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned NewOpc) const;
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2013-10-15 09:48:30 +08:00
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void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned LoOpc, unsigned HiOpc,
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bool HasExplicitDef) const;
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2013-05-17 03:57:23 +08:00
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/// Expand pseudo Int-to-FP conversion instructions.
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///
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/// For example, the following pseudo instruction
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/// PseudoCVT_D32_W D2, A5
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/// gets expanded into these two instructions:
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/// MTC1 F4, A5
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/// CVT_D32_W D2, F4
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///
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/// We do this expansion post-RA to avoid inserting a floating point copy
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/// instruction between MTC1 and CVT_D32_W.
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void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
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2013-05-14 01:43:19 +08:00
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void expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandEhReturn(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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};
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}
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#endif
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