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llvm-project/llvm/test/CodeGen/X86/packss.ll

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[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX --check-prefix=X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64-AVX --check-prefix=X64-AVX2
define <4 x i32> @trunc_ashr_v4i64(<4 x i64> %a) nounwind {
; X32-SSE-LABEL: trunc_ashr_v4i64:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: psrad $31, %xmm1
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X32-SSE-NEXT: psrad $31, %xmm0
; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X32-SSE-NEXT: packsswb %xmm1, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X32-SSE-NEXT: retl
;
; X64-SSE-LABEL: trunc_ashr_v4i64:
; X64-SSE: # BB#0:
; X64-SSE-NEXT: psrad $31, %xmm1
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X64-SSE-NEXT: psrad $31, %xmm0
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-SSE-NEXT: packsswb %xmm1, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-SSE-NEXT: retq
;
; X64-AVX1-LABEL: trunc_ashr_v4i64:
; X64-AVX1: # BB#0:
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
[X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X) Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD. Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal. Differential Revision: https://reviews.llvm.org/D32973 llvm-svn: 302525
2017-05-09 21:14:40 +08:00
; X64-AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; X64-AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; X64-AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: trunc_ashr_v4i64:
; X64-AVX2: # BB#0:
[X86] SET0 to use XMM registers where possible PR26018 PR32862 Differential Revision: https://reviews.llvm.org/D35839 llvm-svn: 309298
2017-07-28 01:47:01 +08:00
; X64-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
[X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X) Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD. Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal. Differential Revision: https://reviews.llvm.org/D32973 llvm-svn: 302525
2017-05-09 21:14:40 +08:00
; X64-AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
%1 = ashr <4 x i64> %a, <i64 63, i64 63, i64 63, i64 63>
%2 = trunc <4 x i64> %1 to <4 x i32>
ret <4 x i32> %2
}
define <8 x i16> @trunc_ashr_v8i32(<8 x i32> %a) nounwind {
; X32-SSE-LABEL: trunc_ashr_v8i32:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: psrad $31, %xmm1
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X32-SSE-NEXT: psrad $31, %xmm0
; X32-SSE-NEXT: packsswb %xmm1, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X32-SSE-NEXT: retl
;
; X64-SSE-LABEL: trunc_ashr_v8i32:
; X64-SSE: # BB#0:
; X64-SSE-NEXT: psrad $31, %xmm1
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-SSE-NEXT: psrad $31, %xmm0
; X64-SSE-NEXT: packsswb %xmm1, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-SSE-NEXT: retq
;
; X64-AVX1-LABEL: trunc_ashr_v8i32:
; X64-AVX1: # BB#0:
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vpsrad $31, %xmm1, %xmm1
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
; X64-AVX2-LABEL: trunc_ashr_v8i32:
; X64-AVX2: # BB#0:
; X64-AVX2-NEXT: vpsrad $31, %ymm0, %ymm0
[X86][SSE] Allow PACKSS to be used to truncate any type of all/none sign bits input At the moment we only use truncateVectorCompareWithPACKSS with direct vector comparison results (just one example of a known all/none signbits input). This change relaxes the direct matching of a SETCC opcode by moving the logic up into SelectionDAG::ComputeNumSignBits and accepting any input with a known splatted signbit. llvm-svn: 287535
2016-11-21 20:05:49 +08:00
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-AVX2-NEXT: vzeroupper
; X64-AVX2-NEXT: retq
%1 = ashr <8 x i32> %a, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
%2 = trunc <8 x i32> %1 to <8 x i16>
ret <8 x i16> %2
}
define <8 x i16> @trunc_ashr_v4i32_icmp_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; X32-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: psrad $31, %xmm0
; X32-SSE-NEXT: pcmpgtd {{\.LCPI.*}}, %xmm1
[SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcode llvm-svn: 287541
2016-11-21 22:36:19 +08:00
; X32-SSE-NEXT: packsswb %xmm1, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X32-SSE-NEXT: retl
;
; X64-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X64-SSE: # BB#0:
; X64-SSE-NEXT: psrad $31, %xmm0
; X64-SSE-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
[SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcode llvm-svn: 287541
2016-11-21 22:36:19 +08:00
; X64-SSE-NEXT: packsswb %xmm1, %xmm0
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
; X64-SSE-NEXT: retq
;
[SelectionDAG] Add ComputeNumSignBits support for CONCAT_VECTORS opcode llvm-svn: 287541
2016-11-21 22:36:19 +08:00
; X64-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X64-AVX: # BB#0:
; X64-AVX-NEXT: vpsrad $31, %xmm0, %xmm0
; X64-AVX-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm1
; X64-AVX-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
; X64-AVX-NEXT: retq
[X86][SSE] Add some initial combine tests that could (should?) use PACKSS llvm-svn: 287504
2016-11-21 05:12:49 +08:00
%1 = ashr <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31>
%2 = icmp sgt <4 x i32> %b, <i32 1, i32 16, i32 255, i32 65535>
%3 = sext <4 x i1> %2 to <4 x i32>
%4 = shufflevector <4 x i32> %1, <4 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%5 = trunc <8 x i32> %4 to <8 x i16>
ret <8 x i16> %5
}