2015-01-31 19:17:59 +08:00
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//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// X86 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
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#include "X86.h"
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
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typedef BasicTTIImplBase<X86TTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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2015-02-01 22:01:15 +08:00
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friend BaseT;
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2015-01-31 19:17:59 +08:00
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const X86Subtarget *ST;
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const X86TargetLowering *TLI;
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2015-02-01 22:22:17 +08:00
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const X86Subtarget *getST() const { return ST; }
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2015-02-01 22:01:15 +08:00
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const X86TargetLowering *getTLI() const { return TLI; }
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2015-01-31 19:17:59 +08:00
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public:
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2015-09-17 07:38:13 +08:00
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explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
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2015-07-09 10:08:42 +08:00
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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2015-01-31 19:17:59 +08:00
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/// \name Scalar TTI Implementations
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/// @{
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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/// @}
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Model cache size and associativity in TargetTransformInfo
Summary:
We add the precise cache sizes and associativity for the following Intel
architectures:
- Penry
- Nehalem
- Westmere
- Sandy Bridge
- Ivy Bridge
- Haswell
- Broadwell
- Skylake
- Kabylake
Polly uses since several months a performance model for BLAS computations that
derives optimal cache and register tile sizes from cache and latency
information (based on ideas from "Analytical Modeling Is Enough for High-Performance BLIS", by Tze Meng Low published at TOMS 2016).
While bootstrapping this model, these target values have been kept in Polly.
However, as our implementation is now rather mature, it seems time to teach
LLVM itself about cache sizes.
Interestingly, L1 and L2 cache sizes are pretty constant across
micro-architectures, hence a set of architecture specific default values
seems like a good start. They can be expanded to more target specific values,
in case certain newer architectures require different values. For now a set
of Intel architectures are provided.
Just as a little teaser, for a simple gemm kernel this model allows us to
improve performance from 1.2s to 0.27s. For gemm kernels with less optimal
memory layouts even larger speedups can be reported.
Reviewers: Meinersbur, bollu, singam-sanjay, hfinkel, gareevroman, fhahn, sebpop, efriedma, asb
Reviewed By: fhahn, asb
Subscribers: lsaba, asb, pollydev, llvm-commits
Differential Revision: https://reviews.llvm.org/D37051
llvm-svn: 311647
2017-08-24 17:46:25 +08:00
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/// \name Cache TTI Implementation
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/// @{
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llvm::Optional<unsigned> getCacheSize(
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TargetTransformInfo::CacheLevel Level) const;
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llvm::Optional<unsigned> getCacheAssociativity(
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TargetTransformInfo::CacheLevel Level) const;
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/// @}
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2015-01-31 19:17:59 +08:00
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool Vector);
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2017-04-06 04:51:38 +08:00
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
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2015-05-07 01:12:25 +08:00
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unsigned getMaxInterleaveFactor(unsigned VF);
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2015-08-06 02:08:10 +08:00
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int getArithmeticInstrCost(
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2015-01-31 19:17:59 +08:00
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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[X86] updating TTI costs for arithmetic instructions on X86\SLM arch.
updated instructions:
pmulld, pmullw, pmulhw, mulsd, mulps, mulpd, divss, divps, divsd, divpd, addpd and subpd.
special optimization case which replaces pmulld with pmullw\pmulhw\pshuf seq.
In case if the real operands bitwidth <= 16.
Differential Revision: https://reviews.llvm.org/D28104
llvm-svn: 291657
2017-01-11 16:23:37 +08:00
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>());
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2015-08-06 02:08:10 +08:00
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int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
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2017-04-12 19:49:08 +08:00
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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const Instruction *I = nullptr);
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int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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const Instruction *I = nullptr);
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2015-08-06 02:08:10 +08:00
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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2017-04-12 19:49:08 +08:00
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unsigned AddressSpace, const Instruction *I = nullptr);
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2015-08-06 02:08:10 +08:00
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int getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace);
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2015-12-29 04:10:59 +08:00
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int getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr,
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bool VariableMask, unsigned Alignment);
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2017-01-05 22:03:41 +08:00
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int getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE,
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const SCEV *Ptr);
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2015-01-31 19:17:59 +08:00
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2017-06-07 00:45:25 +08:00
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unsigned getAtomicMemIntrinsicMaxElementSize() const;
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2016-05-24 16:17:50 +08:00
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int getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
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2017-03-14 14:35:36 +08:00
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ArrayRef<Type *> Tys, FastMathFlags FMF,
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unsigned ScalarizationCostPassed = UINT_MAX);
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2016-05-24 16:17:50 +08:00
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int getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
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2017-03-14 14:35:36 +08:00
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ArrayRef<Value *> Args, FastMathFlags FMF,
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unsigned VF = 1);
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2016-05-24 16:17:50 +08:00
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2017-07-31 22:19:32 +08:00
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int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
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bool IsPairwiseForm);
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2015-01-31 19:17:59 +08:00
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2017-09-08 21:49:36 +08:00
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int getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwiseForm,
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bool IsUnsigned);
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2017-01-02 18:37:52 +08:00
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int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
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unsigned Factor, ArrayRef<unsigned> Indices,
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unsigned Alignment, unsigned AddressSpace);
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int getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy,
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unsigned Factor, ArrayRef<unsigned> Indices,
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unsigned Alignment, unsigned AddressSpace);
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2017-06-25 16:26:25 +08:00
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int getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy,
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unsigned Factor, ArrayRef<unsigned> Indices,
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unsigned Alignment, unsigned AddressSpace);
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2017-01-02 18:37:52 +08:00
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2015-08-06 02:08:10 +08:00
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int getIntImmCost(int64_t);
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2015-01-31 19:17:59 +08:00
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2015-08-06 02:08:10 +08:00
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int getIntImmCost(const APInt &Imm, Type *Ty);
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2015-01-31 19:17:59 +08:00
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2017-08-20 20:34:29 +08:00
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unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands);
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2015-08-06 02:08:10 +08:00
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int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
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int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty);
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2017-08-08 03:56:34 +08:00
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bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
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TargetTransformInfo::LSRCost &C2);
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2015-10-19 15:43:38 +08:00
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bool isLegalMaskedLoad(Type *DataType);
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bool isLegalMaskedStore(Type *DataType);
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2015-10-25 23:37:55 +08:00
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bool isLegalMaskedGather(Type *DataType);
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bool isLegalMaskedScatter(Type *DataType);
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2017-09-09 21:38:18 +08:00
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bool hasDivRemOp(Type *DataType, bool IsSigned);
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2015-07-30 06:09:48 +08:00
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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2017-10-30 22:19:33 +08:00
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const TTI::MemCmpExpansionOptions *enableMemCmpExpansion(
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bool IsZeroCmp) const;
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2016-10-21 05:04:31 +08:00
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bool enableInterleavedAccessVectorization();
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2015-12-29 04:10:59 +08:00
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private:
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int getGSScalarCost(unsigned Opcode, Type *DataTy, bool VariableMask,
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unsigned Alignment, unsigned AddressSpace);
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int getGSVectorCost(unsigned Opcode, Type *DataTy, Value *Ptr,
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unsigned Alignment, unsigned AddressSpace);
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2015-01-31 19:17:59 +08:00
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/// @}
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};
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} // end namespace llvm
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#endif
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