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llvm-project/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll

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[mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
2013-03-07 05:32:03 +08:00
; RUN: llc < %s -march=mips -relocation-model=static | \
; RUN: FileCheck %s -check-prefix=STATIC-O32
; RUN: llc < %s -march=mips -relocation-model=pic | \
; RUN: FileCheck %s -check-prefix=PIC-O32
[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point Summary: Two exceptions to this: test/CodeGen/Mips/octeon.ll test/CodeGen/Mips/octeon_popcnt.ll these test extensions to MIPS64 One test is altered for MIPS-IV: test/CodeGen/Mips/mips64countleading.ll Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests that dclo/dclz are not emitted. Four tests fail and are not in this patch: test/CodeGen/Mips/abicalls.ll test/CodeGen/Mips/fcopysign-f32-f64.ll test/CodeGen/Mips/fcopysign.ll test/CodeGen/Mips/stack-alignment.ll Depends on D3343 Reviewers: matheusalmeida, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3344 llvm-svn: 206185
2014-04-15 00:00:28 +08:00
; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips4 | \
Revert "[mips] N64 static relocation model support" This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
2017-01-26 18:46:07 +08:00
; RUN: FileCheck %s -check-prefix=N64
[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point Summary: Two exceptions to this: test/CodeGen/Mips/octeon.ll test/CodeGen/Mips/octeon_popcnt.ll these test extensions to MIPS64 One test is altered for MIPS-IV: test/CodeGen/Mips/mips64countleading.ll Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests that dclo/dclz are not emitted. Four tests fail and are not in this patch: test/CodeGen/Mips/abicalls.ll test/CodeGen/Mips/fcopysign-f32-f64.ll test/CodeGen/Mips/fcopysign.ll test/CodeGen/Mips/stack-alignment.ll Depends on D3343 Reviewers: matheusalmeida, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3344 llvm-svn: 206185
2014-04-15 00:00:28 +08:00
; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips4 | \
Revert "[mips] N64 static relocation model support" This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
2017-01-26 18:46:07 +08:00
; RUN: FileCheck %s -check-prefix=N64
[mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
2013-03-07 05:32:03 +08:00
; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 | \
Revert "[mips] N64 static relocation model support" This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
2017-01-26 18:46:07 +08:00
; RUN: FileCheck %s -check-prefix=N64
[mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
2013-03-07 05:32:03 +08:00
; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips64 | \
Revert "[mips] N64 static relocation model support" This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
2017-01-26 18:46:07 +08:00
; RUN: FileCheck %s -check-prefix=N64
Fix PR7174, a couple o Mips fixes: - Fix a typo for PIC check during jmp table lowering - Also fix the "first jump table basic block is not considered only reachable by fall through" problem, use this ad-hoc solution until I come up with something better. Patch by stetorvs@gmail.com llvm-svn: 108820
2010-07-20 16:37:04 +08:00
define i32 @main() nounwind readnone {
entry:
%x = alloca i32, align 4 ; <i32*> [#uses=2]
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. llvm-svn: 145171
2011-11-27 14:54:59 +08:00
store volatile i32 2, i32* %x, align 4
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load volatile i32, i32* %x, align 4 ; <i32> [#uses=1]
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. llvm-svn: 158419
2012-06-14 04:33:18 +08:00
; STATIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0)
; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]])
; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0)
; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]])
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
; PIC-O32: jr $[[R5]]
Revert "[mips] N64 static relocation model support" This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
2017-01-26 18:46:07 +08:00
; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3
; N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0)
; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]]
; N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]])
; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
; N64: jr $[[R5]]
Fix PR7174, a couple o Mips fixes: - Fix a typo for PIC check during jmp table lowering - Also fix the "first jump table basic block is not considered only reachable by fall through" problem, use this ad-hoc solution until I come up with something better. Patch by stetorvs@gmail.com llvm-svn: 108820
2010-07-20 16:37:04 +08:00
switch i32 %0, label %bb4 [
i32 0, label %bb5
i32 1, label %bb1
i32 2, label %bb2
i32 3, label %bb3
]
bb1: ; preds = %entry
ret i32 2
bb2: ; preds = %entry
ret i32 0
bb3: ; preds = %entry
ret i32 3
bb4: ; preds = %entry
ret i32 4
bb5: ; preds = %entry
ret i32 1
}
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
2012-02-03 12:33:00 +08:00
[MC] Use .p2align instead of .align For historic reasons, the behavior of .align differs between targets. Fortunately, there are alternatives, .p2align and .balign, which make the interpretation of the parameter explicit, and which behave consistently across targets. This patch teaches MC to use .p2align instead of .align, so that people reading code for multiple architectures don't have to remember which way each platform does its .align directive. Differential Revision: http://reviews.llvm.org/D16549 llvm-svn: 258750
2016-01-26 08:03:25 +08:00
; STATIC-O32: .p2align 2
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
2012-02-03 12:33:00 +08:00
; STATIC-O32: $JTI0_0:
; STATIC-O32: .4byte
; STATIC-O32: .4byte
; STATIC-O32: .4byte
; STATIC-O32: .4byte
[MC] Use .p2align instead of .align For historic reasons, the behavior of .align differs between targets. Fortunately, there are alternatives, .p2align and .balign, which make the interpretation of the parameter explicit, and which behave consistently across targets. This patch teaches MC to use .p2align instead of .align, so that people reading code for multiple architectures don't have to remember which way each platform does its .align directive. Differential Revision: http://reviews.llvm.org/D16549 llvm-svn: 258750
2016-01-26 08:03:25 +08:00
; PIC-O32: .p2align 2
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
2012-02-03 12:33:00 +08:00
; PIC-O32: $JTI0_0:
; PIC-O32: .gpword
; PIC-O32: .gpword
Revert "[mips] N64 static relocation model support" This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
2017-01-26 18:46:07 +08:00
; PIC-O32: .gpword
; PIC-O32: .gpword
; N64: .p2align 3
; N64: .LJTI0_0:
; N64: .gpdword
; N64: .gpdword
; N64: .gpdword
; N64: .gpdword
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. llvm-svn: 149668
2012-02-03 12:33:00 +08:00