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llvm-project/llvm/lib/Target/X86/X86.td

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
Fix whitespace and tabs. llvm-svn: 129517
2011-04-14 22:33:36 +08:00
//
Added LLVM copyright header. llvm-svn: 9321
2003-10-21 23:17:13 +08:00
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Fix whitespace and tabs. llvm-svn: 129517
2011-04-14 22:33:36 +08:00
//
Added LLVM copyright header. llvm-svn: 9321
2003-10-21 23:17:13 +08:00
//===----------------------------------------------------------------------===//
Initial checkin of X86.td file llvm-svn: 7510
2003-08-03 23:47:49 +08:00
//
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
// This is a target description file for the Intel i386 architecture, referred
// to here as the "X86" architecture.
Initial checkin of X86.td file llvm-svn: 7510
2003-08-03 23:47:49 +08:00
//
//===----------------------------------------------------------------------===//
transition to using let instead of set llvm-svn: 7564
2003-08-04 12:59:56 +08:00
// Get the target-independent interfaces which we are implementing...
Initial checkin of X86.td file llvm-svn: 7510
2003-08-03 23:47:49 +08:00
//
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. llvm-svn: 59953
2008-11-24 15:34:46 +08:00
include "llvm/Target/Target.td"
Initial checkin of X86.td file llvm-svn: 7510
2003-08-03 23:47:49 +08:00
Add Mode64Bit feature and sink it down to MC layer. llvm-svn: 134641
2011-07-08 05:06:52 +08:00
//===----------------------------------------------------------------------===//
(no commit message) llvm-svn: 162010
2012-08-16 11:50:04 +08:00
// X86 Subtarget state
Add Mode64Bit feature and sink it down to MC layer. llvm-svn: 134641
2011-07-08 05:06:52 +08:00
//
def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
"64-bit mode (x86_64)">;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
//===----------------------------------------------------------------------===//
(no commit message) llvm-svn: 162010
2012-08-16 11:50:04 +08:00
// X86 Subtarget features
Add an "implies" field to features. This indicates that, if the current feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. llvm-svn: 36756
2007-05-05 04:38:40 +08:00
//===----------------------------------------------------------------------===//
Add support for modeling whether or not the processor has support for conditional moves as a subtarget feature. This is the easy part of PR4841. llvm-svn: 80763
2009-09-02 13:53:04 +08:00
def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
"Enable conditional move instructions">;
Add patterns for the x86 popcnt instruction. - Also adds a new POPCNT subtarget feature that is currently enabled if the target supports SSE4.2 (nehalem) or SSE4A (barcelona). llvm-svn: 120917
2010-12-05 04:32:23 +08:00
def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
"Support POPCNT instruction">;
Implement a feature (-vector-unaligned-mem) to allow targets to ignore alignment requirements for SIMD memory operands. This is useful on architectures like the AMD 10h that do not trap on unaligned references if a status bit is twiddled at startup time. llvm-svn: 93151
2010-01-12 00:29:42 +08:00
Add an "implies" field to features. This indicates that, if the current feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. llvm-svn: 36756
2007-05-05 04:38:40 +08:00
def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
"Enable MMX instructions">;
def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
"Enable SSE instructions",
Add support for modeling whether or not the processor has support for conditional moves as a subtarget feature. This is the easy part of PR4841. llvm-svn: 80763
2009-09-02 13:53:04 +08:00
// SSE codegen depends on cmovs, and all
Fix whitespace and tabs. llvm-svn: 129517
2011-04-14 22:33:36 +08:00
// SSE1+ processors support them.
Add support for modeling whether or not the processor has support for conditional moves as a subtarget feature. This is the easy part of PR4841. llvm-svn: 80763
2009-09-02 13:53:04 +08:00
[FeatureMMX, FeatureCMOV]>;
Add an "implies" field to features. This indicates that, if the current feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. llvm-svn: 36756
2007-05-05 04:38:40 +08:00
def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
"Enable SSE2 instructions",
[FeatureSSE1]>;
def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
"Enable SSE3 instructions",
[FeatureSSE2]>;
def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
"Enable SSSE3 instructions",
[FeatureSSE3]>;
SSE 4.1 Intrinsics and detection llvm-svn: 46681
2008-02-03 15:18:54 +08:00
def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
"Enable SSE 4.1 instructions",
[FeatureSSSE3]>;
def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
"Enable SSE 4.2 instructions",
Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. llvm-svn: 147339
2011-12-29 23:51:45 +08:00
[FeatureSSE41]>;
Add an "implies" field to features. This indicates that, if the current feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. llvm-svn: 36756
2007-05-05 04:38:40 +08:00
def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
Add 3DNow! intrinsics. llvm-svn: 129551
2011-04-15 08:32:41 +08:00
"Enable 3DNow! instructions",
[FeatureMMX]>;
Add an "implies" field to features. This indicates that, if the current feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. llvm-svn: 36756
2007-05-05 04:38:40 +08:00
def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX. llvm-svn: 36860
2007-05-06 15:56:19 +08:00
"Enable 3DNow! Athlon instructions",
[Feature3DNow]>;
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has SSE2, however it's possible to disable SSE2, and the subtarget support code thinks that if 64-bit implies SSE2 and SSE2 is disabled then 64-bit should also be disabled. Instead, just mark all the 64-bit subtargets as explicitly supporting SSE2. Also, move the code that makes -march=x86-64 enable 64-bit support by default to only apply when there is no explicit subtarget. If you need to specify a subtarget and you want 64-bit code, you'll need to select a subtarget that supports 64-bit code. llvm-svn: 63575
2009-02-03 08:04:43 +08:00
// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
// without disabling 64-bit mode.
3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and I assume MMX. llvm-svn: 36860
2007-05-06 15:56:19 +08:00
def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
all 64-bit cpus have cmov, this should fix CodeGen/X86/cmov.ll (at least) on non-x86 builders. llvm-svn: 98520
2010-03-15 06:24:34 +08:00
"Support 64-bit instructions",
[FeatureCMOV]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
"64-bit with cmpxchg16b",
[Feature64Bit]>;
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. llvm-svn: 61557
2009-01-02 13:35:45 +08:00
def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
"Bit testing of memory is slow">;
Nehalem unaligned memory access is fast. llvm-svn: 100089
2010-04-01 13:58:17 +08:00
def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
"IsUAMemFast", "true",
"Fast unaligned memory access">;
Update CPU capabilities for AMD machines - added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and barcelona with appropriate sse3/4a levels - added FeatureSSE4A for amdfam10 processors in X86Subtarget: - added hasSSE4A - updated AutoDetectSubtargetFeatures to detect SSE4A - updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and family 10h as amdfam10 New processor names match those used by gcc. Patch by Paul Redmond! llvm-svn: 72434
2009-05-27 05:04:35 +08:00
def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. llvm-svn: 147369
2011-12-30 15:16:00 +08:00
"Support SSE 4a instructions",
[FeatureSSE3]>;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior. llvm-svn: 147770
2012-01-09 17:02:13 +08:00
def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
"Enable AVX instructions",
[FeatureSSE42]>;
def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. llvm-svn: 143319
2011-10-31 03:57:21 +08:00
"Enable AVX2 instructions",
[FeatureAVX]>;
X86: Rename the CLMUL target feature to PCLMUL. It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. llvm-svn: 157745
2012-05-31 22:34:17 +08:00
def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
"Enable packed carry-less multiplication instructions",
Make CLMUL and AES imply SSE2 since its needed to legalize the type. llvm-svn: 155888
2012-05-01 13:28:32 +08:00
[FeatureSSE2]>;
Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang. llvm-svn: 157903
2012-06-04 02:58:46 +08:00
def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. llvm-svn: 147349
2011-12-30 03:46:19 +08:00
"Enable three-operand fused multiple-add",
[FeatureAVX]>;
Add feature flags for AVX and FMA and fix some SSE4A feature flag initialization problems. llvm-svn: 74350
2009-06-27 06:46:54 +08:00
def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. llvm-svn: 147369
2011-12-30 15:16:00 +08:00
"Enable four-operand fused multiple-add",
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. llvm-svn: 155897
2012-05-01 14:54:48 +08:00
[FeatureAVX, FeatureSSE4A]>;
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. llvm-svn: 147369
2011-12-30 15:16:00 +08:00
def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
Make XOP imply AVX as its needed to legalize the registers types. llvm-svn: 155891
2012-05-01 13:41:41 +08:00
"Enable XOP instructions",
Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well. llvm-svn: 162012
2012-08-16 12:04:02 +08:00
[FeatureFMA4]>;
Implement a feature (-vector-unaligned-mem) to allow targets to ignore alignment requirements for SIMD memory operands. This is useful on architectures like the AMD 10h that do not trap on unaligned references if a status bit is twiddled at startup time. llvm-svn: 93151
2010-01-12 00:29:42 +08:00
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
"HasVectorUAMem", "true",
"Allow unaligned memory operands on vector/SIMD instructions">;
Separate out the AES-NI instructions from the SSE4.2 instructions. Add a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. llvm-svn: 100231
2010-04-03 05:54:27 +08:00
def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
Make CLMUL and AES imply SSE2 since its needed to legalize the type. llvm-svn: 155888
2012-05-01 13:28:32 +08:00
"Enable AES instructions",
[FeatureSSE2]>;
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
2011-10-04 01:28:23 +08:00
def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
"Support MOVBE instruction">;
def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
"Support RDRAND instruction">;
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. llvm-svn: 141505
2011-10-09 15:31:39 +08:00
def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
"Support 16-bit floating point conversion instructions">;
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. llvm-svn: 143319
2011-10-31 03:57:21 +08:00
def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
"Support FS/GS Base instructions">;
Add X86 LZCNT instruction. Including instruction selection support. llvm-svn: 141651
2011-10-11 14:44:02 +08:00
def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
"Support LZCNT instruction">;
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
"Support BMI instructions">;
Add X86 BZHI instruction as well as BMI2 feature detection. llvm-svn: 142122
2011-10-16 15:55:05 +08:00
def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
"Support BMI2 instructions">;
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
"Support RTM instructions">;
added basic support for Intel ADX instructions -feature flag, instructions definitions, test cases llvm-svn: 175196
2013-02-15 03:08:21 +08:00
def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
"Support ADX instructions">;
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang. llvm-svn: 150008
2012-02-08 06:50:41 +08:00
def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
"Use LEA for adjusting the stack pointer">;
Generic Bypass Slow Div - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150
2012-09-05 02:22:17 +08:00
def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
Pad Short Functions for Intel Atom The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. llvm-svn: 171879
2013-01-09 02:27:24 +08:00
"HasSlowDivide", "true",
"Use small divide for positive values less than 256">;
def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
"PadShortFunctions", "true",
"Pad short functions">;
Add feature flags for AVX and FMA and fix some SSE4A feature flag initialization problems. llvm-svn: 74350
2009-06-27 06:46:54 +08:00
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
//===----------------------------------------------------------------------===//
// X86 processors supported.
//===----------------------------------------------------------------------===//
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00
include "X86Schedule.td"
def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
"Intel Atom processors">;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
class Proc<string Name, list<SubtargetFeature> Features>
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
: ProcessorModel<Name, GenericModel, Features>;
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00
class AtomProc<string Name, list<SubtargetFeature> Features>
I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-07-07 12:00:00 +08:00
: ProcessorModel<Name, AtomModel, Features>;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
def : Proc<"generic", []>;
def : Proc<"i386", []>;
def : Proc<"i486", []>;
Accept -march=i586, because gcc does (a synonym for pentium). Fixes gcc.target/i386/20000720-1.c gcc.target/i386/pr26826.c llvm-svn: 57528
2008-10-15 06:06:33 +08:00
def : Proc<"i586", []>;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
def : Proc<"pentium", []>;
def : Proc<"pentium-mmx", [FeatureMMX]>;
def : Proc<"i686", []>;
Add support for modeling whether or not the processor has support for conditional moves as a subtarget feature. This is the easy part of PR4841. llvm-svn: 80763
2009-09-02 13:53:04 +08:00
def : Proc<"pentiumpro", [FeatureCMOV]>;
def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
We only need to specify the most-implied feature for an architecture. llvm-svn: 37275
2007-05-22 13:15:37 +08:00
def : Proc<"pentium3", [FeatureSSE1]>;
Add pentium{3,4}m cpus. Patch by Alexander Best! llvm-svn: 130749
2011-05-03 11:42:50 +08:00
def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. llvm-svn: 61557
2009-01-02 13:35:45 +08:00
def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
We only need to specify the most-implied feature for an architecture. llvm-svn: 37275
2007-05-22 13:15:37 +08:00
def : Proc<"pentium4", [FeatureSSE2]>;
Add pentium{3,4}m cpus. Patch by Alexander Best! llvm-svn: 130749
2011-05-03 11:42:50 +08:00
def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
Make '-mtune=x86_64' assume fast unaligned memory accesses. Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. Reviewed by Dan Gohman. llvm-svn: 170269
2012-12-15 17:01:13 +08:00
def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
FeatureFastUAMem]>;
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. llvm-svn: 91910
2009-12-23 01:47:23 +08:00
def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B,
FeatureSlowBTMem]>;
def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
FeatureSlowBTMem]>;
def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
FeatureSlowBTMem]>;
Atom has SIMD instruction set extension up to SSSE3 llvm-svn: 166665
2012-10-25 15:06:48 +08:00
def : AtomProc<"atom", [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
Generic Bypass Slow Div - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150
2012-09-05 02:22:17 +08:00
FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
Pad Short Functions for Intel Atom The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. llvm-svn: 171879
2013-01-09 02:27:24 +08:00
FeatureSlowDivide, FeaturePadShortFunctions]>;
Separate out the AES-NI instructions from the SSE4.2 instructions. Add a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. llvm-svn: 100231
2010-04-03 05:54:27 +08:00
// "Arrandale" along with corei3 and corei5
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. llvm-svn: 147347
2011-12-30 02:47:31 +08:00
FeatureSlowBTMem, FeatureFastUAMem,
FeaturePOPCNT, FeatureAES]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B,
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. llvm-svn: 147347
2011-12-30 02:47:31 +08:00
FeatureSlowBTMem, FeatureFastUAMem,
FeaturePOPCNT]>;
Separate out the AES-NI instructions from the SSE4.2 instructions. Add a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. llvm-svn: 100231
2010-04-03 05:54:27 +08:00
// Westmere is a similar machine to nehalem with some additional features.
// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. llvm-svn: 147347
2011-12-30 02:47:31 +08:00
FeatureSlowBTMem, FeatureFastUAMem,
X86: Rename the CLMUL target feature to PCLMUL. It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. llvm-svn: 157745
2012-05-31 22:34:17 +08:00
FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. llvm-svn: 141571
2011-10-11 03:35:07 +08:00
// Sandy Bridge
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. llvm-svn: 121439
2010-12-10 08:26:57 +08:00
// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
// rather than a superset.
Address a FIXME and update the fast unaligned memory feature for newer Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. llvm-svn: 169730
2012-12-10 17:18:44 +08:00
def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. llvm-svn: 141571
2011-10-11 03:35:07 +08:00
// Ivy Bridge
Address a FIXME and update the fast unaligned memory feature for newer Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. llvm-svn: 169730
2012-12-10 17:18:44 +08:00
def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. llvm-svn: 143319
2011-10-31 03:57:21 +08:00
FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
// Haswell
Address a FIXME and update the fast unaligned memory feature for newer Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. llvm-svn: 169730
2012-12-10 17:18:44 +08:00
def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
FeatureRDRAND, FeatureF16C, FeatureFSGSBase,
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. llvm-svn: 147347
2011-12-30 02:47:31 +08:00
FeatureMOVBE, FeatureLZCNT, FeatureBMI,
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
2012-11-08 15:28:54 +08:00
FeatureBMI2, FeatureFMA,
FeatureRTM]>;
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. llvm-svn: 141939
2011-10-14 11:21:46 +08:00
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
def : Proc<"k6", [FeatureMMX]>;
Add 3DNow! intrinsics. llvm-svn: 129551
2011-04-15 08:32:41 +08:00
def : Proc<"k6-2", [Feature3DNow]>;
def : Proc<"k6-3", [Feature3DNow]>;
def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. llvm-svn: 61557
2009-01-02 13:35:45 +08:00
def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has SSE2, however it's possible to disable SSE2, and the subtarget support code thinks that if 64-bit implies SSE2 and SSE2 is disabled then 64-bit should also be disabled. Instead, just mark all the 64-bit subtargets as explicitly supporting SSE2. Also, move the code that makes -march=x86-64 enable 64-bit support by default to only apply when there is no explicit subtarget. If you need to specify a subtarget and you want 64-bit code, you'll need to select a subtarget that supports 64-bit code. llvm-svn: 63575
2009-02-03 08:04:43 +08:00
def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
FeatureSlowBTMem]>;
def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
FeatureSlowBTMem]>;
def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
FeatureSlowBTMem]>;
def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
FeatureSlowBTMem]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
Update CPU capabilities for AMD machines - added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and barcelona with appropriate sse3/4a levels - added FeatureSSE4A for amdfam10 processors in X86Subtarget: - added hasSSE4A - updated AutoDetectSubtargetFeatures to detect SSE4A - updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and family 10h as amdfam10 New processor names match those used by gcc. Patch by Paul Redmond! llvm-svn: 72434
2009-05-27 05:04:35 +08:00
FeatureSlowBTMem]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
Update CPU capabilities for AMD machines - added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and barcelona with appropriate sse3/4a levels - added FeatureSSE4A for amdfam10 processors in X86Subtarget: - added hasSSE4A - updated AutoDetectSubtargetFeatures to detect SSE4A - updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and family 10h as amdfam10 New processor names match those used by gcc. Patch by Paul Redmond! llvm-svn: 72434
2009-05-27 05:04:35 +08:00
FeatureSlowBTMem]>;
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660
2011-08-27 05:21:21 +08:00
def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
Update CPU capabilities for AMD machines - added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and barcelona with appropriate sse3/4a levels - added FeatureSSE4A for amdfam10 processors in X86Subtarget: - added hasSSE4A - updated AutoDetectSubtargetFeatures to detect SSE4A - updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and family 10h as amdfam10 New processor names match those used by gcc. Patch by Paul Redmond! llvm-svn: 72434
2009-05-27 05:04:35 +08:00
FeatureSlowBTMem]>;
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. llvm-svn: 155897
2012-05-01 14:54:48 +08:00
def : Proc<"amdfam10", [FeatureSSE4A,
X86: Turns out bulldozer also supports sse42 and lzcnt. While at it remove the barcelona/instanbul/shanghai subtargets, they're unsupported by GCC and look pretty broken. llvm-svn: 145494
2011-11-30 23:48:16 +08:00
Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. llvm-svn: 147347
2011-12-30 02:47:31 +08:00
FeaturePOPCNT, FeatureSlowBTMem]>;
Add definitions for AMD's bobcat (aka btver1) llvm-svn: 147846
2012-01-10 19:50:02 +08:00
// Bobcat
def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
FeatureLZCNT, FeaturePOPCNT]>;
// Bulldozer
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. llvm-svn: 155897
2012-05-01 14:54:48 +08:00
def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
X86: Rename the CLMUL target feature to PCLMUL. It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. llvm-svn: 157745
2012-05-31 22:34:17 +08:00
FeatureAES, FeaturePCLMUL,
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. llvm-svn: 155897
2012-05-01 14:54:48 +08:00
FeatureLZCNT, FeaturePOPCNT]>;
Add definitions for AMD's bobcat (aka btver1) llvm-svn: 147846
2012-01-10 19:50:02 +08:00
// Enhanced Bulldozer
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. llvm-svn: 155897
2012-05-01 14:54:48 +08:00
def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
X86: Rename the CLMUL target feature to PCLMUL. It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. llvm-svn: 157745
2012-05-31 22:34:17 +08:00
FeatureAES, FeaturePCLMUL,
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list. llvm-svn: 155897
2012-05-01 14:54:48 +08:00
FeatureF16C, FeatureLZCNT,
Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well. llvm-svn: 162012
2012-08-16 12:04:02 +08:00
FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
Add support for AMD Geode. llvm-svn: 163710
2012-09-12 22:36:02 +08:00
def : Proc<"geode", [Feature3DNowA]>;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
def : Proc<"winchip-c6", [FeatureMMX]>;
Add 3DNow! intrinsics. llvm-svn: 129551
2011-04-15 08:32:41 +08:00
def : Proc<"winchip2", [Feature3DNow]>;
def : Proc<"c3", [Feature3DNow]>;
We only need to specify the most-implied feature for an architecture. llvm-svn: 37275
2007-05-22 13:15:37 +08:00
def : Proc<"c3-2", [FeatureSSE1]>;
Still need to support -mcpu=<> or cross compilation will fail. Doh. llvm-svn: 30764
2006-10-06 17:17:41 +08:00
Initial checkin of X86.td file llvm-svn: 7510
2003-08-03 23:47:49 +08:00
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "X86RegisterInfo.td"
Add Target class for X86 target llvm-svn: 7523
2003-08-04 02:19:37 +08:00
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
Add new TableGen instruction definitions llvm-svn: 7537
2003-08-04 05:54:21 +08:00
include "X86InstrInfo.td"
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
2010-04-05 11:10:20 +08:00
def X86InstrInfo : InstrInfo;
Add Target class for X86 target llvm-svn: 7523
2003-08-04 02:19:37 +08:00
Add a description of the X86-64 calling convention and the return conventions. This doesn't do anything yet, but may in the future. llvm-svn: 34636
2007-02-27 02:17:14 +08:00
//===----------------------------------------------------------------------===//
// Calling Conventions
//===----------------------------------------------------------------------===//
include "X86CallingConv.td"
//===----------------------------------------------------------------------===//
Clean up comments. llvm-svn: 117785
2010-10-30 21:48:28 +08:00
// Assembly Parser
Add a description of the X86-64 calling convention and the return conventions. This doesn't do anything yet, but may in the future. llvm-svn: 34636
2007-02-27 02:17:14 +08:00
//===----------------------------------------------------------------------===//
Match X86 register names to number. llvm-svn: 77404
2009-07-29 08:02:19 +08:00
def ATTAsmParser : AsmParser {
Rename X86ATTAsmParser -> X86AsmParser We are using one parser to parse att as well as intel style syntax. llvm-svn: 148032
2012-01-13 02:03:40 +08:00
string AsmParserClassName = "AsmParser";
Split AsmParser into two components - AsmParser and AsmParserVariant AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
2012-01-10 03:13:28 +08:00
}
def ATTAsmParserVariant : AsmParserVariant {
Match X86 register names to number. llvm-svn: 77404
2009-07-29 08:02:19 +08:00
int Variant = 0;
llvm-mc/AsmParser: Allow target to specific a comment delimiter, which will be used to strip hard coded comments out of .td assembly strings. llvm-svn: 78716
2009-08-12 04:59:47 +08:00
// Discard comments in assembly strings.
string CommentDelimiter = "#";
// Recognize hard coded registers.
string RegisterPrefix = "%";
Match X86 register names to number. llvm-svn: 77404
2009-07-29 08:02:19 +08:00
}
Add definition for intel asm variant. Right now, this just adds additional entries in match table. The parser does not use them yet. llvm-svn: 147859
2012-01-11 01:51:54 +08:00
def IntelAsmParserVariant : AsmParserVariant {
int Variant = 1;
// Discard comments in assembly strings.
string CommentDelimiter = ";";
// Recognize hard coded registers.
string RegisterPrefix = "";
}
Clean up comments. llvm-svn: 117785
2010-10-30 21:48:28 +08:00
//===----------------------------------------------------------------------===//
// Assembly Printers
//===----------------------------------------------------------------------===//
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
2004-10-04 04:36:57 +08:00
// The X86 target supports two different syntaxes for emitting machine code.
// This is controlled by the -x86-asm-syntax={att|intel}
def ATTAsmWriter : AsmWriter {
split MCInst printing out of the X86ATTInstPrinter class into its own X86ATTInstPrinter class. The inst printer now has just one dependence on the code generator (TRI). llvm-svn: 81703
2009-09-14 03:30:11 +08:00
string AsmWriterClassName = "ATTInstPrinter";
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
2004-10-04 04:36:57 +08:00
int Variant = 0;
Clean up asm writer usage for x86 and msp430 to flag that the writer should use MC instructions in the printInstruction() method via the tablegen flag for it rather than a #define prior to including the autogenerated bits. llvm-svn: 115238
2010-10-01 07:40:25 +08:00
bit isMCAsmWriter = 1;
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
2004-10-04 04:36:57 +08:00
}
def IntelAsmWriter : AsmWriter {
remove a temporary hack. llvm-svn: 82395
2009-09-20 15:47:59 +08:00
string AsmWriterClassName = "IntelInstPrinter";
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
2004-10-04 04:36:57 +08:00
int Variant = 1;
Clean up asm writer usage for x86 and msp430 to flag that the writer should use MC instructions in the printInstruction() method via the tablegen flag for it rather than a #define prior to including the autogenerated bits. llvm-svn: 115238
2010-10-01 07:40:25 +08:00
bit isMCAsmWriter = 1;
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
2004-10-04 04:36:57 +08:00
}
Add Target class for X86 target llvm-svn: 7523
2003-08-04 02:19:37 +08:00
def X86 : Target {
// Information about the instructions...
transition to using let instead of set llvm-svn: 7564
2003-08-04 12:59:56 +08:00
let InstructionSet = X86InstrInfo;
Match X86 register names to number. llvm-svn: 77404
2009-07-29 08:02:19 +08:00
let AssemblyParsers = [ATTAsmParser];
Add definition for intel asm variant. Right now, this just adds additional entries in match table. The parser does not use them yet. llvm-svn: 147859
2012-01-11 01:51:54 +08:00
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
2004-10-04 04:36:57 +08:00
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
Add Target class for X86 target llvm-svn: 7523
2003-08-04 02:19:37 +08:00
}