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llvm-project/clang/test/CodeGen/aarch64-neon-shifts.c

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[ARM64] Allow the disabling of NEON and crypto instructions. Update tests to pass -target-feature +neon. llvm-svn: 206394
2014-04-16 23:33:48 +08:00
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
IRGen: Add optnone attribute on function during O0 Amongst other, this will help LTO to correctly handle/honor files compiled with O0, helping debugging failures. It also seems in line with how we handle other options, like how -fnoinline adds the appropriate attribute as well. Differential Revision: https://reviews.llvm.org/D28404 llvm-svn: 304127
2017-05-29 13:38:20 +08:00
// RUN: -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
Do not emit undefined lsrh/ashr for NEON shifts These IR instructions are undefined when the amount is equal to operand size, but NEON right shifts support such shifts. Work around that by emitting a different IR in these cases. llvm-svn: 191953
2013-10-04 21:13:15 +08:00
#include <arm_neon.h>
uint8x8_t test_shift_vshr(uint8x8_t a) {
// CHECK-LABEL: test_shift_vshr
Don't assume instruction names in the output. llvm-svn: 191957
2013-10-04 22:42:00 +08:00
// CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
Do not emit undefined lsrh/ashr for NEON shifts These IR instructions are undefined when the amount is equal to operand size, but NEON right shifts support such shifts. Work around that by emitting a different IR in these cases. llvm-svn: 191953
2013-10-04 21:13:15 +08:00
return vshr_n_u8(a, 5);
}
int8x8_t test_shift_vshr_smax(int8x8_t a) {
// CHECK-LABEL: test_shift_vshr_smax
Don't assume instruction names in the output. llvm-svn: 191957
2013-10-04 22:42:00 +08:00
// CHECK: %{{.*}} = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
Do not emit undefined lsrh/ashr for NEON shifts These IR instructions are undefined when the amount is equal to operand size, but NEON right shifts support such shifts. Work around that by emitting a different IR in these cases. llvm-svn: 191953
2013-10-04 21:13:15 +08:00
return vshr_n_s8(a, 8);
}
uint8x8_t test_shift_vshr_umax(uint8x8_t a) {
// CHECK-LABEL: test_shift_vshr_umax
// CHECK: ret <8 x i8> zeroinitializer
return vshr_n_u8(a, 8);
}
uint8x8_t test_shift_vsra(uint8x8_t a, uint8x8_t b) {
// CHECK-LABEL: test_shift_vsra
Don't assume instruction names in the output. llvm-svn: 191957
2013-10-04 22:42:00 +08:00
// CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations. This is mostly a one-time autoconversion of tests that checked assembly after "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This should make them much more stable to changes in LLVM so they won't break on unrelated changes. "opt -mem2reg" is a compromise designed to increase the readability of tests that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is stable enough that no surpises will come along. Should address http://llvm.org/PR26815. llvm-svn: 263048
2016-03-10 02:54:42 +08:00
// CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
Do not emit undefined lsrh/ashr for NEON shifts These IR instructions are undefined when the amount is equal to operand size, but NEON right shifts support such shifts. Work around that by emitting a different IR in these cases. llvm-svn: 191953
2013-10-04 21:13:15 +08:00
return vsra_n_u8(a, b, 5);
}
int8x8_t test_shift_vsra_smax(int8x8_t a, int8x8_t b) {
// CHECK-LABEL: test_shift_vsra_smax
Don't assume instruction names in the output. llvm-svn: 191957
2013-10-04 22:42:00 +08:00
// CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations. This is mostly a one-time autoconversion of tests that checked assembly after "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This should make them much more stable to changes in LLVM so they won't break on unrelated changes. "opt -mem2reg" is a compromise designed to increase the readability of tests that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is stable enough that no surpises will come along. Should address http://llvm.org/PR26815. llvm-svn: 263048
2016-03-10 02:54:42 +08:00
// CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
Do not emit undefined lsrh/ashr for NEON shifts These IR instructions are undefined when the amount is equal to operand size, but NEON right shifts support such shifts. Work around that by emitting a different IR in these cases. llvm-svn: 191953
2013-10-04 21:13:15 +08:00
return vsra_n_s8(a, b, 8);
}
uint8x8_t test_shift_vsra_umax(uint8x8_t a, uint8x8_t b) {
// CHECK-LABEL: test_shift_vsra_umax
ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations. This is mostly a one-time autoconversion of tests that checked assembly after "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This should make them much more stable to changes in LLVM so they won't break on unrelated changes. "opt -mem2reg" is a compromise designed to increase the readability of tests that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is stable enough that no surpises will come along. Should address http://llvm.org/PR26815. llvm-svn: 263048
2016-03-10 02:54:42 +08:00
// CHECK: [[RES:%.*]] = add <8 x i8> %a, zeroinitializer
// CHECK: ret <8 x i8> [[RES]]
Do not emit undefined lsrh/ashr for NEON shifts These IR instructions are undefined when the amount is equal to operand size, but NEON right shifts support such shifts. Work around that by emitting a different IR in these cases. llvm-svn: 191953
2013-10-04 21:13:15 +08:00
return vsra_n_u8(a, b, 8);
}