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llvm-project/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll

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Change the fast-isel-abort option from bool to int to enable "levels" Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
2015-02-28 02:32:11 +08:00
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
[PowerPC] More fast-isel chunks (returns and integer extends) Incremental improvement to fast-isel for PPC64. This allows us to select on ret, sext, and zext. Filling in sext/zext improves some of the existing logic in handling compare-immediates that needed extends. A simplified return convention for fast-isel is also added to the PPC64 calling conventions. All call/return processing for DAG selection is handled with custom code, so there isn't an existing CC to rely on here. The include of PPCGenCallingConv.inc causes compiler warnings due to the 32-bit calling conventions that are not used, so the dummy function "usePPC32CCs()" is added here to silence those. Test cases for the return and extend logic are added. llvm-svn: 189266
2013-08-27 03:42:51 +08:00
; zext
define i32 @zext_8_32(i8 %a) nounwind ssp {
; ELF64: zext_8_32
%r = zext i8 %a to i32
; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
ret i32 %r
}
define i32 @zext_16_32(i16 %a) nounwind ssp {
; ELF64: zext_16_32
%r = zext i16 %a to i32
; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
ret i32 %r
}
define i64 @zext_8_64(i8 %a) nounwind ssp {
; ELF64: zext_8_64
%r = zext i8 %a to i64
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
ret i64 %r
}
define i64 @zext_16_64(i16 %a) nounwind ssp {
; ELF64: zext_16_64
%r = zext i16 %a to i64
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
ret i64 %r
}
define i64 @zext_32_64(i32 %a) nounwind ssp {
; ELF64: zext_32_64
%r = zext i32 %a to i64
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
ret i64 %r
}
; sext
define i32 @sext_8_32(i8 %a) nounwind ssp {
; ELF64: sext_8_32
%r = sext i8 %a to i32
; ELF64: extsb
ret i32 %r
}
define i32 @sext_16_32(i16 %a) nounwind ssp {
; ELF64: sext_16_32
%r = sext i16 %a to i32
; ELF64: extsh
ret i32 %r
}
define i64 @sext_8_64(i8 %a) nounwind ssp {
; ELF64: sext_8_64
%r = sext i8 %a to i64
; ELF64: extsb
ret i64 %r
}
define i64 @sext_16_64(i16 %a) nounwind ssp {
; ELF64: sext_16_64
%r = sext i16 %a to i64
; ELF64: extsh
ret i64 %r
}
define i64 @sext_32_64(i32 %a) nounwind ssp {
; ELF64: sext_32_64
%r = sext i32 %a to i64
; ELF64: extsw
ret i64 %r
}