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llvm-project/llvm/test/CodeGen/ARM/misched-copy-arm.ll

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MI Sched: eliminate local vreg copies. For now, we just reschedule instructions that use the copied vregs and let regalloc elliminate it. I would really like to eliminate the copies on-the-fly during scheduling, but we need a complete implementation of repairIntervalsInRange() first. The general strategy is for the register coalescer to eliminate as many global copies as possible and shrink live ranges to be extended-basic-block local. The coalescer should not have to worry about resolving local copies (e.g. it shouldn't attemp to reorder instructions). The scheduler is a much better place to deal with local interference. The coalescer side of this equation needs work. llvm-svn: 180193
2013-04-24 23:54:43 +08:00
; REQUIRES: asserts
ARM & AArch64: make use of common cmpxchg idioms after expansion The C and C++ semantics for compare_exchange require it to return a bool indicating success. This gets mapped to LLVM IR which follows each cmpxchg with an icmp of the value loaded against the desired value. When lowered to ldxr/stxr loops, this extra comparison is redundant: its results are implicit in the control-flow of the function. This commit makes two changes: it replaces that icmp with appropriate PHI nodes, and then makes sure earlyCSE is called after expansion to actually make use of the opportunities revealed. I've also added -{arm,aarch64}-enable-atomic-tidy options, so that existing fragile tests aren't perturbed too much by the change. Many of them either rely on undef/unreachable too pervasively to be restored to something well-defined (particularly while making sure they test the same obscure assert from many years ago), or depend on a particular CFG shape, which is disrupted by SimplifyCFG. rdar://problem/16227836 llvm-svn: 209883
2014-05-30 18:09:59 +08:00
; RUN: llc -mtriple=thumb-eabi -mcpu=swift -pre-RA-sched=source -join-globalcopies -enable-misched -verify-misched -debug-only=misched -arm-atomic-cfg-tidy=0 %s -o - 2>&1 | FileCheck %s
MI Sched: eliminate local vreg copies. For now, we just reschedule instructions that use the copied vregs and let regalloc elliminate it. I would really like to eliminate the copies on-the-fly during scheduling, but we need a complete implementation of repairIntervalsInRange() first. The general strategy is for the register coalescer to eliminate as many global copies as possible and shrink live ranges to be extended-basic-block local. The coalescer should not have to worry about resolving local copies (e.g. it shouldn't attemp to reorder instructions). The scheduler is a much better place to deal with local interference. The coalescer side of this equation needs work. llvm-svn: 180193
2013-04-24 23:54:43 +08:00
;
; Loop counter copies should be eliminated.
; There is also a MUL here, but we don't care where it is scheduled.
; CHECK: postinc
; CHECK: *** Final schedule for BB#2 ***
; CHECK: t2LDRs
; CHECK: t2ADDrr
; CHECK: t2CMPrr
; CHECK: COPY
define i32 @postinc(i32 %a, i32* nocapture %d, i32 %s) nounwind {
entry:
%cmp4 = icmp eq i32 %a, 0
br i1 %cmp4, label %for.end, label %for.body
for.body: ; preds = %entry, %for.body
%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
%s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ]
%indvars.iv.next = add i32 %indvars.iv, %s
%arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv
%0 = load i32* %arrayidx, align 4
%mul = mul nsw i32 %0, %s.05
%exitcond = icmp eq i32 %indvars.iv.next, %a
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
%s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ]
ret i32 %s.0.lcssa
}
MI Sched fix: assert "Disconnected LRG within the scheduling region." llvm-svn: 187435
2013-07-31 03:59:08 +08:00
; This case was a crasher in constrainLocalCopy.
; The problem was the t2LDR_PRE defining both the global and local lrg.
; CHECK-LABEL: *** Final schedule for BB#5 ***
This test may have been sensitive to the ARM ABI... llvm-svn: 187442
2013-07-31 04:34:59 +08:00
; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
MI Sched fix: assert "Disconnected LRG within the scheduling region." llvm-svn: 187435
2013-07-31 03:59:08 +08:00
; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
; CHECK-LABEL: MACHINEINSTRS
%struct.rtx_def = type { [4 x i8], [1 x %union.rtunion_def] }
%union.rtunion_def = type { i64 }
; Function Attrs: nounwind ssp
declare hidden fastcc void @df_ref_record(i32* nocapture, %struct.rtx_def*, %struct.rtx_def**, %struct.rtx_def*, i32, i32) #0
; Function Attrs: nounwind ssp
define hidden fastcc void @df_def_record_1(i32* nocapture %df, %struct.rtx_def* %x, %struct.rtx_def* %insn) #0 {
entry:
br label %while.cond
while.cond: ; preds = %if.end28, %entry
%loc.0 = phi %struct.rtx_def** [ %rtx31, %if.end28 ], [ undef, %entry ]
%dst.0 = phi %struct.rtx_def* [ %0, %if.end28 ], [ undef, %entry ]
switch i32 undef, label %if.end47 [
i32 61, label %if.then46
i32 64, label %if.then24
i32 132, label %if.end28
i32 133, label %if.end28
]
if.then24: ; preds = %while.cond
br label %if.end28
if.end28: ; preds = %if.then24, %while.cond, %while.cond
%dst.1 = phi %struct.rtx_def* [ undef, %if.then24 ], [ %dst.0, %while.cond ], [ %dst.0, %while.cond ]
%arrayidx30 = getelementptr inbounds %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0
%rtx31 = bitcast %union.rtunion_def* %arrayidx30 to %struct.rtx_def**
TBAA: remove !tbaa from testing cases when they are not needed. llvm-svn: 191689
2013-10-01 02:17:35 +08:00
%0 = load %struct.rtx_def** %rtx31, align 4
MI Sched fix: assert "Disconnected LRG within the scheduling region." llvm-svn: 187435
2013-07-31 03:59:08 +08:00
br label %while.cond
if.then46: ; preds = %while.cond
tail call fastcc void @df_ref_record(i32* %df, %struct.rtx_def* %dst.0, %struct.rtx_def** %loc.0, %struct.rtx_def* %insn, i32 0, i32 undef)
unreachable
if.end47: ; preds = %while.cond
ret void
}
attributes #0 = { nounwind ssp }