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llvm-project/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll

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Change the fast-isel-abort option from bool to int to enable "levels" Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
2015-02-28 02:32:11 +08:00
; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
define void @t0(i32 %a) nounwind {
entry:
; CHECK: t0
; CHECK: str {{w[0-9]+}}, [sp, #12]
; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
; CHECK-NEXT: str [[REGISTER]], [sp, #12]
; CHECK: ret
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr
%tmp = load i32* %a.addr
store i32 %tmp, i32* %a.addr
ret void
}
define void @t1(i64 %a) nounwind {
; CHECK: t1
; CHECK: str {{x[0-9]+}}, [sp, #8]
; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
; CHECK-NEXT: str [[REGISTER]], [sp, #8]
; CHECK: ret
%a.addr = alloca i64, align 4
store i64 %a, i64* %a.addr
%tmp = load i64* %a.addr
store i64 %tmp, i64* %a.addr
ret void
}
define zeroext i1 @i1(i1 %a) nounwind {
entry:
; CHECK: @i1
; CHECK: and w0, w0, #0x1
; CHECK: strb w0, [sp, #15]
; CHECK: ldrb w0, [sp, #15]
; CHECK: and w0, w0, #0x1
; CHECK: and w0, w0, #0x1
; CHECK: add sp, sp, #16
; CHECK: ret
%a.addr = alloca i1, align 1
store i1 %a, i1* %a.addr, align 1
%0 = load i1* %a.addr, align 1
ret i1 %0
}
define i32 @t2(i32 *%ptr) nounwind {
entry:
; CHECK-LABEL: t2:
; CHECK: ldur w0, [x0, #-4]
; CHECK: ret
%0 = getelementptr i32 *%ptr, i32 -1
%1 = load i32* %0, align 4
ret i32 %1
}
define i32 @t3(i32 *%ptr) nounwind {
entry:
; CHECK-LABEL: t3:
; CHECK: ldur w0, [x0, #-256]
; CHECK: ret
%0 = getelementptr i32 *%ptr, i32 -64
%1 = load i32* %0, align 4
ret i32 %1
}
define void @t4(i32 *%ptr) nounwind {
entry:
; CHECK-LABEL: t4:
[FastISel][AArch64] Use the zero register for stores. Use the zero register directly when possible to avoid an unnecessary register copy and a wasted register at -O0. This also uses integer stores to store a positive floating-point zero. This saves us from materializing the positive zero in a register and then storing it. llvm-svn: 216617
2014-08-28 05:04:52 +08:00
; CHECK: stur wzr, [x0, #-4]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%0 = getelementptr i32 *%ptr, i32 -1
store i32 0, i32* %0, align 4
ret void
}
define void @t5(i32 *%ptr) nounwind {
entry:
; CHECK-LABEL: t5:
[FastISel][AArch64] Use the zero register for stores. Use the zero register directly when possible to avoid an unnecessary register copy and a wasted register at -O0. This also uses integer stores to store a positive floating-point zero. This saves us from materializing the positive zero in a register and then storing it. llvm-svn: 216617
2014-08-28 05:04:52 +08:00
; CHECK: stur wzr, [x0, #-256]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%0 = getelementptr i32 *%ptr, i32 -64
store i32 0, i32* %0, align 4
ret void
}
define void @t6() nounwind {
; CHECK: t6
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
2014-04-30 19:19:28 +08:00
; CHECK: brk #0x1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
tail call void @llvm.trap()
ret void
}
declare void @llvm.trap() nounwind