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[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
2018-08-15 04:21:05 +08:00
// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-feature +avx512f -o - | FileCheck %s
typedef long long __m128i __attribute__ ((vector_size (16)));
typedef long long __m256i __attribute__ ((vector_size (32)));
typedef long long __m512i __attribute__ ((vector_size (64)));
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK: define <2 x i64> @testXMMout(<2 x i64>* %p) #0
[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
2018-08-15 04:21:05 +08:00
__m128i testXMMout(__m128i *p) {
__m128i xmm0;
__asm__("vmovdqu %1, %0" :"=v"(xmm0) : "m"(*(__m128i*)p));
return xmm0;
}
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK: define <4 x i64> @testYMMout(<4 x i64>* %p) #1
[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
2018-08-15 04:21:05 +08:00
__m256i testYMMout(__m256i *p) {
__m256i ymm0;
__asm__("vmovdqu %1, %0" :"=v"(ymm0) : "m"(*(__m256i*)p));
return ymm0;
}
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK: define <8 x i64> @testZMMout(<8 x i64>* %p) #2
[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
2018-08-15 04:21:05 +08:00
__m512i testZMMout(__m512i *p) {
__m512i zmm0;
__asm__("vmovdqu64 %1, %0" :"=v"(zmm0) : "m"(*(__m512i*)p));
return zmm0;
}
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK: define void @testXMMin(<2 x i64> %xmm0, <2 x i64>* %p) #0
[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
2018-08-15 04:21:05 +08:00
void testXMMin(__m128i xmm0, __m128i *p) {
__asm__("vmovdqu %0, %1" : : "v"(xmm0), "m"(*(__m128i*)p));
}
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK: define void @testYMMin(<4 x i64> %ymm0, <4 x i64>* %p) #1
[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
2018-08-15 04:21:05 +08:00
void testYMMin(__m256i ymm0, __m256i *p) {
__asm__("vmovdqu %0, %1" : : "v"(ymm0), "m"(*(__m256i*)p));
}
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK: define void @testZMMin(<8 x i64> %zmm0, <8 x i64>* %p) #2
[InlineAsm] Update the min-legal-vector-width function attribute based on inputs and outputs to inline assembly Summary: Another piece of my ongoing to work for prefer-vector-width. min-legal-vector-width will eventually be used by the X86 backend to know whether it needs to make 512 bits type legal when prefer-vector-width=256. If the user used inline assembly that passed in/out a 512-bit register, we need to make sure 512 bits are considered legal. Otherwise we'll get an assert failure when we try to wire up the inline assembly to the rest of the code. This patch just checks the LLVM IR types to see if they are vectors and then updates the attribute based on their total width. I'm not sure if this is the best way to do this or if there's any subtlety I might have missed. So if anyone has other opinions on how to do this I'm open to suggestions. Reviewers: chandlerc, rsmith, rnk Reviewed By: rnk Subscribers: eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D50678 llvm-svn: 339721
2018-08-15 04:21:05 +08:00
void testZMMin(__m512i zmm0, __m512i *p) {
__asm__("vmovdqu64 %0, %1" : : "v"(zmm0), "m"(*(__m512i*)p));
}
// CHECK: attributes #0 = {{.*}}"min-legal-vector-width"="128"
// CHECK: attributes #1 = {{.*}}"min-legal-vector-width"="256"
// CHECK: attributes #2 = {{.*}}"min-legal-vector-width"="512"