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llvm-project/clang/test/CodeGen/arm64-microsoft-status-reg.cpp

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[COFF, ARM64] Enable unit test arm64-microsoft-status-reg.cpp only for aarch64 target This should unbreak bots broken here: http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/14391 http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/38288 llvm-svn: 344767
2018-10-19 08:05:26 +08:00
// REQUIRES: aarch64-registered-target
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
[clang][ARM] Fix msvc arm{64} builtins to use int on LP64 systems. The `InterlockedX_{acq,nf,rel}` functions deal with 32 bits which is long on MSVC, but int on most other systems. This also checks that `ReadStatusRegister` and `WriteStatusRegister` have the correct type on aarch64-darwin. Differential Revision: https://reviews.llvm.org/D64164 llvm-svn: 367479
2019-08-01 04:42:28 +08:00
// RUN: %clang_cc1 -triple arm64-darwin -fms-compatibility -emit-llvm -S \
// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
[clang][ARM] Fix msvc arm{64} builtins to use int on LP64 systems. The `InterlockedX_{acq,nf,rel}` functions deal with 32 bits which is long on MSVC, but int on most other systems. This also checks that `ReadStatusRegister` and `WriteStatusRegister` have the correct type on aarch64-darwin. Differential Revision: https://reviews.llvm.org/D64164 llvm-svn: 367479
2019-08-01 04:42:28 +08:00
// RUN: %clang_cc1 -triple arm64-darwin -fms-compatibility -emit-llvm \
// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
// From winnt.h
#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
( ((op0 & 1) << 14) | \
((op1 & 7) << 11) | \
((crn & 15) << 7) | \
((crm & 15) << 3) | \
((op2 & 7) << 0) )
#define ARM64_CNTVCT ARM64_SYSREG(3,3,14, 0,2) // Generic Timer counter register
#define ARM64_PMCCNTR_EL0 ARM64_SYSREG(3,3, 9,13,0) // Cycle Count Register [CP15_PMCCNTR]
#define ARM64_PMSELR_EL0 ARM64_SYSREG(3,3, 9,12,5) // Event Counter Selection Register [CP15_PMSELR]
#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2) // Event Count Register [CP15_PMXEVCNTR]
#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8) // Direct Event Count Register [n/a]
#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2) // Thread ID Register, User Read/Write [CP15_TPIDRURW]
#define ARM64_TPIDRRO_EL0 ARM64_SYSREG(3,3,13, 0,3) // Thread ID Register, User Read Only [CP15_TPIDRURO]
#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4) // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// From intrin.h
__int64 _ReadStatusReg(int);
void _WriteStatusReg(int, __int64);
void check_ReadWriteStatusReg(__int64 v) {
__int64 ret;
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_CNTVCT);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, CNTVCT_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, PMCCNTR_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_PMSELR_EL0);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, PMSELR_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_TPIDR_EL0);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, TPIDR_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, TPIDRRO_EL0
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
ret = _ReadStatusReg(ARM64_TPIDR_EL1);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: mrs x8, TPIDR_EL1
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_CNTVCT, v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr S3_3_C14_C0_2, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_PMCCNTR_EL0, v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr PMCCNTR_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_PMSELR_EL0, v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr PMSELR_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr PMXEVCNTR_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr PMEVCNTR0_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr PMEVCNTR1_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr PMEVCNTR30_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_TPIDR_EL0, v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr TPIDR_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_TPIDRRO_EL0, v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr TPIDRRO_EL0, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD10:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
_WriteStatusReg(ARM64_TPIDR_EL1, v);
Fix CodeGen/arm64-microsoft-status-reg.cpp test Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8. Reviewers: arsenm, MatzeB, efriedma Reviewed By: efriedma Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59557 llvm-svn: 356517
2019-03-20 04:55:14 +08:00
// CHECK-ASM: msr TPIDR_EL1, x8
[COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 llvm-svn: 353493
2019-02-08 09:17:49 +08:00
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD11:.*]], i64 %[[VAR]])
[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
2018-10-19 07:35:35 +08:00
}
// CHECK-IR: ![[MD2]] = !{!"3:3:14:0:2"}
// CHECK-IR: ![[MD3]] = !{!"3:3:9:13:0"}
// CHECK-IR: ![[MD4]] = !{!"3:3:9:12:5"}
// CHECK-IR: ![[MD5]] = !{!"3:3:9:13:2"}
// CHECK-IR: ![[MD6]] = !{!"3:3:14:8:0"}
// CHECK-IR: ![[MD7]] = !{!"3:3:14:8:1"}
// CHECK-IR: ![[MD8]] = !{!"3:3:14:11:6"}
// CHECK-IR: ![[MD9]] = !{!"3:3:13:0:2"}
// CHECK-IR: ![[MD10]] = !{!"3:3:13:0:3"}
// CHECK-IR: ![[MD11]] = !{!"3:0:13:0:4"}