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llvm-project/llvm/test/CodeGen/X86/divide-by-constant.ll

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[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu | FileCheck %s --check-prefix=X64
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
Add a couple dag combines to transform mulhi/mullo into a wider multiply when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
2010-12-13 16:39:01 +08:00
define zeroext i16 @test1(i16 zeroext %x) nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test1:
; X32: # BB#0: # %entry
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: imull $63551, %eax, %eax # imm = 0xF83F
; X32-NEXT: shrl $21, %eax
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
;
; X64-LABEL: test1:
; X64: # BB#0: # %entry
; X64-NEXT: imull $63551, %edi, %eax # imm = 0xF83F
; X64-NEXT: shrl $21, %eax
; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
entry:
Add a couple dag combines to transform mulhi/mullo into a wider multiply when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
2010-12-13 16:39:01 +08:00
%div = udiv i16 %x, 33
ret i16 %div
}
define zeroext i16 @test2(i8 signext %x, i16 zeroext %c) nounwind readnone ssp noredzone {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test2:
; X32: # BB#0: # %entry
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: imull $43691, %eax, %eax # imm = 0xAAAB
; X32-NEXT: shrl $17, %eax
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
;
; X64-LABEL: test2:
; X64: # BB#0: # %entry
; X64-NEXT: imull $43691, %esi, %eax # imm = 0xAAAB
; X64-NEXT: shrl $17, %eax
; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
Add a couple dag combines to transform mulhi/mullo into a wider multiply when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
2010-12-13 16:39:01 +08:00
entry:
%div = udiv i16 %c, 3
ret i16 %div
}
define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) nounwind readnone ssp noredzone {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test3:
; X32: # BB#0: # %entry
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: imull $171, %eax, %eax
; X32-NEXT: shrl $9, %eax
[x86] swap order of srl (and X, C1), C2 when it saves size The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely. As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this in the backend. Differential Revision: https://reviews.llvm.org/D38181 llvm-svn: 314023
2017-09-23 03:37:21 +08:00
; X32-NEXT: movzwl %ax, %eax
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; X32-NEXT: retl
;
; X64-LABEL: test3:
; X64: # BB#0: # %entry
; X64-NEXT: imull $171, %esi, %eax
; X64-NEXT: shrl $9, %eax
[x86] swap order of srl (and X, C1), C2 when it saves size The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely. As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this in the backend. Differential Revision: https://reviews.llvm.org/D38181 llvm-svn: 314023
2017-09-23 03:37:21 +08:00
; X64-NEXT: movzwl %ax, %eax
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; X64-NEXT: retq
Add a couple dag combines to transform mulhi/mullo into a wider multiply when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
2010-12-13 16:39:01 +08:00
entry:
%div = udiv i8 %c, 3
ret i8 %div
}
define signext i16 @test4(i16 signext %x) nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test4:
; X32: # BB#0: # %entry
; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
; X32-NEXT: imull $1986, %eax, %eax # imm = 0x7C2
; X32-NEXT: movl %eax, %ecx
; X32-NEXT: shrl $31, %ecx
; X32-NEXT: shrl $16, %eax
; X32-NEXT: addl %ecx, %eax
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
;
; X64-LABEL: test4:
; X64: # BB#0: # %entry
; X64-NEXT: imull $1986, %edi, %eax # imm = 0x7C2
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: shrl $31, %ecx
; X64-NEXT: shrl $16, %eax
; X64-NEXT: addl %ecx, %eax
; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
Add a couple dag combines to transform mulhi/mullo into a wider multiply when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
2010-12-13 16:39:01 +08:00
entry:
%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
ret i16 %div
}
merge two tests llvm-svn: 121847
2010-12-15 13:58:59 +08:00
define i32 @test5(i32 %A) nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test5:
; X32: # BB#0:
; X32-NEXT: movl $365384439, %eax # imm = 0x15C752F7
; X32-NEXT: mull {{[0-9]+}}(%esp)
; X32-NEXT: shrl $27, %edx
; X32-NEXT: movl %edx, %eax
; X32-NEXT: retl
;
; X64-LABEL: test5:
; X64: # BB#0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: imulq $365384439, %rax, %rax # imm = 0x15C752F7
; X64-NEXT: shrq $59, %rax
; X64-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
; X64-NEXT: retq
merge two tests llvm-svn: 121847
2010-12-15 13:58:59 +08:00
%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
ret i32 %tmp1
}
Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
2011-01-31 00:38:43 +08:00
define signext i16 @test6(i16 signext %x) nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test6:
; X32: # BB#0: # %entry
; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
; X32-NEXT: imull $26215, %eax, %eax # imm = 0x6667
; X32-NEXT: movl %eax, %ecx
; X32-NEXT: shrl $31, %ecx
; X32-NEXT: sarl $18, %eax
; X32-NEXT: addl %ecx, %eax
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
;
; X64-LABEL: test6:
; X64: # BB#0: # %entry
; X64-NEXT: imull $26215, %edi, %eax # imm = 0x6667
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: shrl $31, %ecx
; X64-NEXT: sarl $18, %eax
; X64-NEXT: addl %ecx, %eax
; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
2011-01-31 00:38:43 +08:00
entry:
%div = sdiv i16 %x, 10
ret i16 %div
}
BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
2011-03-18 04:39:14 +08:00
define i32 @test7(i32 %x) nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test7:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shrl $2, %eax
; X32-NEXT: movl $613566757, %ecx # imm = 0x24924925
; X32-NEXT: mull %ecx
; X32-NEXT: movl %edx, %eax
; X32-NEXT: retl
;
; X64-LABEL: test7:
; X64: # BB#0:
; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; X64-NEXT: shrl $2, %edi
; X64-NEXT: imulq $613566757, %rdi, %rax # imm = 0x24924925
; X64-NEXT: shrq $32, %rax
; X64-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
; X64-NEXT: retq
BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
2011-03-18 04:39:14 +08:00
%div = udiv i32 %x, 28
ret i32 %div
}
PR13326: Fix a subtle edge case in the udiv -> magic multiply generator. This caused 6 of 65k possible 8 bit udivs to be wrong. llvm-svn: 160058
2012-07-12 02:31:59 +08:00
; PR13326
define i8 @test8(i8 %x) nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test8:
; X32: # BB#0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: shrb %al
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: imull $211, %eax, %eax
; X32-NEXT: shrl $13, %eax
[x86] swap order of srl (and X, C1), C2 when it saves size The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely. As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this in the backend. Differential Revision: https://reviews.llvm.org/D38181 llvm-svn: 314023
2017-09-23 03:37:21 +08:00
; X32-NEXT: movzwl %ax, %eax
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; X32-NEXT: retl
;
; X64-LABEL: test8:
; X64: # BB#0:
; X64-NEXT: shrb %dil
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: imull $211, %eax, %eax
; X64-NEXT: shrl $13, %eax
[x86] swap order of srl (and X, C1), C2 when it saves size The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely. As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this in the backend. Differential Revision: https://reviews.llvm.org/D38181 llvm-svn: 314023
2017-09-23 03:37:21 +08:00
; X64-NEXT: movzwl %ax, %eax
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; X64-NEXT: retq
PR13326: Fix a subtle edge case in the udiv -> magic multiply generator. This caused 6 of 65k possible 8 bit udivs to be wrong. llvm-svn: 160058
2012-07-12 02:31:59 +08:00
%div = udiv i8 %x, 78
ret i8 %div
}
define i8 @test9(i8 %x) nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: test9:
; X32: # BB#0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: shrb $2, %al
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: imull $71, %eax, %eax
; X32-NEXT: shrl $11, %eax
[x86] swap order of srl (and X, C1), C2 when it saves size The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely. As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this in the backend. Differential Revision: https://reviews.llvm.org/D38181 llvm-svn: 314023
2017-09-23 03:37:21 +08:00
; X32-NEXT: movzwl %ax, %eax
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; X32-NEXT: retl
;
; X64-LABEL: test9:
; X64: # BB#0:
; X64-NEXT: shrb $2, %dil
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: imull $71, %eax, %eax
; X64-NEXT: shrl $11, %eax
[x86] swap order of srl (and X, C1), C2 when it saves size The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. There are also better improvements based on known-bits that allow us to eliminate the mask entirely. As noted, this could be extended. There are potentially other wins from always shifting first, but doing that reveals a tangle of problems in other pattern matching. We do this transform generically in instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this in the backend. Differential Revision: https://reviews.llvm.org/D38181 llvm-svn: 314023
2017-09-23 03:37:21 +08:00
; X64-NEXT: movzwl %ax, %eax
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; X64-NEXT: retq
PR13326: Fix a subtle edge case in the udiv -> magic multiply generator. This caused 6 of 65k possible 8 bit udivs to be wrong. llvm-svn: 160058
2012-07-12 02:31:59 +08:00
%div = udiv i8 %x, 116
ret i8 %div
}
[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245431
2015-08-19 19:21:43 +08:00
define i32 @testsize1(i32 %x) minsize nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: testsize1:
; X32: # BB#0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pushl $32
; X32-NEXT: popl %ecx
; X32-NEXT: cltd
; X32-NEXT: idivl %ecx
; X32-NEXT: retl
;
; X64-LABEL: testsize1:
; X64: # BB#0: # %entry
; X64-NEXT: pushq $32
; X64-NEXT: popq %rcx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: cltd
; X64-NEXT: idivl %ecx
; X64-NEXT: retq
[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245431
2015-08-19 19:21:43 +08:00
entry:
%div = sdiv i32 %x, 32
ret i32 %div
}
define i32 @testsize2(i32 %x) minsize nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: testsize2:
; X32: # BB#0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pushl $33
; X32-NEXT: popl %ecx
; X32-NEXT: cltd
; X32-NEXT: idivl %ecx
; X32-NEXT: retl
;
; X64-LABEL: testsize2:
; X64: # BB#0: # %entry
; X64-NEXT: pushq $33
; X64-NEXT: popq %rcx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: cltd
; X64-NEXT: idivl %ecx
; X64-NEXT: retq
[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245431
2015-08-19 19:21:43 +08:00
entry:
%div = sdiv i32 %x, 33
ret i32 %div
}
define i32 @testsize3(i32 %x) minsize nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: testsize3:
; X32: # BB#0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shrl $5, %eax
; X32-NEXT: retl
;
; X64-LABEL: testsize3:
; X64: # BB#0: # %entry
; X64-NEXT: shrl $5, %edi
; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245431
2015-08-19 19:21:43 +08:00
entry:
%div = udiv i32 %x, 32
ret i32 %div
}
define i32 @testsize4(i32 %x) minsize nounwind {
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets llvm-svn: 287104
2016-11-16 22:12:11 +08:00
; X32-LABEL: testsize4:
; X32: # BB#0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pushl $33
; X32-NEXT: popl %ecx
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: divl %ecx
; X32-NEXT: retl
;
; X64-LABEL: testsize4:
; X64: # BB#0: # %entry
; X64-NEXT: pushq $33
; X64-NEXT: popq %rcx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: divl %ecx
; X64-NEXT: retq
[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245431
2015-08-19 19:21:43 +08:00
entry:
%div = udiv i32 %x, 33
ret i32 %div
}
[X86] Add integer division test for PR23590 Shows missed opportunity to recognise reduced integer division result size llvm-svn: 287110
2016-11-16 22:54:34 +08:00
define i64 @PR23590(i64 %x) nounwind {
; X32-LABEL: PR23590:
; X32: # BB#0: # %entry
; X32-NEXT: subl $12, %esp
; X32-NEXT: pushl $0
; X32-NEXT: pushl $12345 # imm = 0x3039
; X32-NEXT: pushl {{[0-9]+}}(%esp)
; X32-NEXT: pushl {{[0-9]+}}(%esp)
; X32-NEXT: calll __umoddi3
; X32-NEXT: addl $16, %esp
; X32-NEXT: pushl $0
; X32-NEXT: pushl $7
; X32-NEXT: pushl %edx
; X32-NEXT: pushl %eax
; X32-NEXT: calll __udivdi3
; X32-NEXT: addl $28, %esp
; X32-NEXT: retl
;
; X64-LABEL: PR23590:
; X64: # BB#0: # %entry
; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: movabsq $6120523590596543007, %rdx # imm = 0x54F077C718E7C21F
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"" This crashes on boringSSL on PPC (will send reduced testcase) This reverts commit r312328. llvm-svn: 312490
2017-09-04 23:47:00 +08:00
; X64-NEXT: movq %rcx, %rax
[X86] Add integer division test for PR23590 Shows missed opportunity to recognise reduced integer division result size llvm-svn: 287110
2016-11-16 22:54:34 +08:00
; X64-NEXT: mulq %rdx
; X64-NEXT: shrq $12, %rdx
; X64-NEXT: imulq $12345, %rdx, %rax # imm = 0x3039
; X64-NEXT: subq %rax, %rcx
; X64-NEXT: movabsq $2635249153387078803, %rdx # imm = 0x2492492492492493
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: mulq %rdx
; X64-NEXT: subq %rdx, %rcx
; X64-NEXT: shrq %rcx
; X64-NEXT: leaq (%rcx,%rdx), %rax
; X64-NEXT: shrq $2, %rax
; X64-NEXT: retq
entry:
%rem = urem i64 %x, 12345
%div = udiv i64 %rem, 7
ret i64 %div
}