2007-01-19 15:51:42 +08:00
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//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-01-19 15:51:42 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARM specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMSubtarget.h"
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#include "ARMGenSubtarget.inc"
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2011-01-12 05:46:47 +08:00
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#include "ARMBaseRegisterInfo.h"
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2009-08-29 07:18:09 +08:00
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#include "llvm/GlobalValue.h"
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2009-06-23 05:01:46 +08:00
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#include "llvm/Support/CommandLine.h"
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2009-11-10 08:48:55 +08:00
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#include "llvm/ADT/SmallVector.h"
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2007-01-19 15:51:42 +08:00
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using namespace llvm;
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2009-06-23 05:01:46 +08:00
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static cl::opt<bool>
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ReserveR9("arm-reserve-r9", cl::Hidden,
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cl::desc("Reserve R9, making it unavailable as GPR"));
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2009-11-24 08:44:37 +08:00
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static cl::opt<bool>
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2011-01-22 02:55:51 +08:00
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DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
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2009-11-24 08:44:37 +08:00
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2010-09-28 12:09:35 +08:00
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static cl::opt<bool>
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StrictAlign("arm-strict-align", cl::Hidden,
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cl::desc("Disallow all unaligned memory accesses"));
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2011-06-30 09:53:36 +08:00
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ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool isT)
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2010-03-07 03:39:36 +08:00
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: ARMArchVersion(V4)
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2010-09-10 09:29:16 +08:00
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, ARMProcFamily(Others)
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2009-05-24 03:51:43 +08:00
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, ARMFPUType(None)
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2010-03-26 07:47:34 +08:00
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, UseNEONForSinglePrecisionFP(false)
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2010-12-06 06:04:16 +08:00
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, SlowFPVMLx(false)
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2011-04-01 17:20:31 +08:00
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, HasVMLxForwarding(false)
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2010-08-10 03:19:36 +08:00
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, SlowFPBrcc(false)
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2009-10-16 14:11:08 +08:00
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, IsThumb(isT)
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2009-06-02 04:00:48 +08:00
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, ThumbMode(Thumb1)
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2010-08-11 15:17:46 +08:00
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, NoARM(false)
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2009-09-30 08:10:16 +08:00
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, PostRAScheduler(false)
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2009-06-23 05:01:46 +08:00
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, IsR9Reserved(ReserveR9)
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2011-01-17 16:03:18 +08:00
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, UseMovt(false)
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2010-03-15 02:42:38 +08:00
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, HasFP16(false)
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2010-10-13 00:22:47 +08:00
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, HasD16(false)
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2010-05-06 07:44:43 +08:00
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, HasHardwareDivide(false)
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, HasT2ExtractPack(false)
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2010-08-11 14:22:01 +08:00
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, HasDataBarrier(false)
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2010-08-10 03:19:36 +08:00
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, Pref32BitThumb(false)
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2011-04-20 02:11:49 +08:00
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, AvoidCPSRPartialUpdate(false)
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2010-11-03 14:34:55 +08:00
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, HasMPExtension(false)
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2010-08-11 23:44:15 +08:00
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, FPOnlySP(false)
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2010-09-28 12:09:35 +08:00
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, AllowsUnalignedMem(false)
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2007-02-14 03:52:28 +08:00
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, stackAlignment(4)
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2011-06-30 09:53:36 +08:00
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, CPUString(CPU)
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2011-01-12 05:46:47 +08:00
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, TargetTriple(TT)
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2007-02-14 03:52:28 +08:00
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, TargetABI(ARM_ABI_APCS) {
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2007-01-19 15:51:42 +08:00
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// Determine default and user specified characteristics
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2010-03-07 03:39:36 +08:00
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// When no arch is specified either by CPU or by attributes, make the default
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// ARMv4T.
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2010-11-10 06:50:47 +08:00
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const char *ARMArchFeature = "";
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2011-06-30 09:53:36 +08:00
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if (CPUString.empty())
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CPUString = "generic";
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2010-11-10 06:50:47 +08:00
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if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
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2010-03-07 03:39:36 +08:00
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ARMArchVersion = V4T;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v4t";
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2010-11-10 06:50:47 +08:00
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}
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2010-03-07 03:39:36 +08:00
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2007-01-19 15:51:42 +08:00
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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2009-03-08 12:02:49 +08:00
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unsigned Len = TT.length();
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2009-03-10 04:25:39 +08:00
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unsigned Idx = 0;
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2009-05-30 07:41:08 +08:00
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2009-03-10 04:25:39 +08:00
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if (Len >= 5 && TT.substr(0, 4) == "armv")
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Idx = 4;
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2009-06-23 05:28:22 +08:00
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else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
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2009-06-02 04:00:48 +08:00
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IsThumb = true;
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2009-03-10 04:25:39 +08:00
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if (Len >= 7 && TT[5] == 'v')
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Idx = 6;
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}
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if (Idx) {
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unsigned SubVer = TT[Idx];
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2010-03-07 03:39:36 +08:00
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if (SubVer >= '7' && SubVer <= '9') {
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ARMArchVersion = V7A;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v7a";
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2010-11-10 06:50:47 +08:00
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if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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2010-05-06 04:44:35 +08:00
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ARMArchVersion = V7M;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v7m";
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2010-11-10 06:50:47 +08:00
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}
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2010-03-07 03:39:36 +08:00
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} else if (SubVer == '6') {
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ARMArchVersion = V6;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v6";
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2010-11-10 06:50:47 +08:00
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
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2010-03-07 03:39:36 +08:00
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ARMArchVersion = V6T2;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v6t2";
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2010-11-10 06:50:47 +08:00
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}
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2010-03-07 03:39:36 +08:00
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} else if (SubVer == '5') {
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ARMArchVersion = V5T;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v5t";
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2010-11-10 06:50:47 +08:00
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
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2010-03-07 03:39:36 +08:00
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ARMArchVersion = V5TE;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v5te";
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2010-11-10 06:50:47 +08:00
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}
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2010-03-07 03:39:36 +08:00
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} else if (SubVer == '4') {
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2010-11-10 06:50:47 +08:00
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if (Len >= Idx+2 && TT[Idx+1] == 't') {
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2010-03-07 03:39:36 +08:00
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ARMArchVersion = V4T;
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2011-06-30 09:53:36 +08:00
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ARMArchFeature = "+v4t";
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2010-11-10 06:50:47 +08:00
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} else {
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2010-03-07 03:39:36 +08:00
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ARMArchVersion = V4;
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2010-11-10 06:50:47 +08:00
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ARMArchFeature = "";
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}
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2009-03-08 12:02:49 +08:00
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}
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}
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2007-02-14 03:52:28 +08:00
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if (TT.find("eabi") != std::string::npos)
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TargetABI = ARM_ABI_AAPCS;
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2011-06-30 10:12:44 +08:00
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// Insert the architecture feature derived from the target triple into the
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// feature string. This is important for setting features that are implied
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// based on the architecture version.
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std::string FSWithArch = std::string(ARMArchFeature);
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if (FSWithArch.empty())
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2010-11-10 06:50:47 +08:00
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FSWithArch = FS;
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2011-06-30 10:12:44 +08:00
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else if (!FS.empty())
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FSWithArch = FSWithArch + "," + FS;
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2011-06-30 09:53:36 +08:00
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ParseSubtargetFeatures(FSWithArch, CPUString);
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2010-11-10 06:50:47 +08:00
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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// After parsing Itineraries, set ItinData.IssueWidth.
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computeIssueWidth();
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2010-11-10 06:50:47 +08:00
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// Thumb2 implies at least V6T2.
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if (ARMArchVersion >= V6T2)
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ThumbMode = Thumb2;
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else if (ThumbMode >= Thumb2)
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ARMArchVersion = V6T2;
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2007-02-14 03:52:28 +08:00
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if (isAAPCS_ABI())
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stackAlignment = 8;
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2011-01-17 16:03:18 +08:00
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if (!isTargetDarwin())
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UseMovt = hasV6T2Ops();
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else {
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2009-06-23 05:01:46 +08:00
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IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
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2011-01-22 02:55:51 +08:00
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UseMovt = DarwinUseMOVT && hasV6T2Ops();
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2011-01-17 16:03:18 +08:00
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}
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2009-10-02 05:46:35 +08:00
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2009-10-16 14:11:08 +08:00
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if (!isThumb() || hasThumb2())
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PostRAScheduler = true;
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2010-09-28 12:09:35 +08:00
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// v6+ may or may not support unaligned mem access depending on the system
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// configuration.
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if (!StrictAlign && hasV6Ops() && isTargetDarwin())
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AllowsUnalignedMem = true;
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2007-01-19 15:51:42 +08:00
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}
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2009-08-29 07:18:09 +08:00
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/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
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2009-09-03 15:04:02 +08:00
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bool
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2010-04-15 09:51:59 +08:00
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ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
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Reloc::Model RelocM) const {
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2009-09-03 15:04:02 +08:00
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if (RelocM == Reloc::Static)
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2009-08-29 07:18:09 +08:00
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return false;
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2009-09-03 15:04:02 +08:00
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2010-01-28 04:34:15 +08:00
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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2011-02-22 14:58:34 +08:00
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bool isDecl = GV->hasAvailableExternallyLinkage();
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if (GV->isDeclaration() && !GV->isMaterializable())
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isDecl = true;
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2009-09-03 15:04:02 +08:00
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if (!isTargetDarwin()) {
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return false;
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return true;
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} else {
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if (RelocM == Reloc::PIC_) {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage())
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// Hidden $non_lazy_ptr reference.
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return true;
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return false;
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} else {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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2010-12-24 12:28:06 +08:00
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2009-09-03 15:04:02 +08:00
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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}
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}
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return false;
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2009-08-29 07:18:09 +08:00
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}
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2009-11-10 08:48:55 +08:00
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2010-09-29 05:57:50 +08:00
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unsigned ARMSubtarget::getMispredictionPenalty() const {
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// If we have a reasonable estimate of the pipeline depth, then we can
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// estimate the penalty of a misprediction based on that.
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if (isCortexA8())
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return 13;
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else if (isCortexA9())
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return 8;
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2010-12-24 12:28:06 +08:00
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2010-09-29 05:57:50 +08:00
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// Otherwise, just return a sensible default.
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return 10;
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}
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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void ARMSubtarget::computeIssueWidth() {
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unsigned allStage1Units = 0;
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for (const InstrItinerary *itin = InstrItins.Itineraries;
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itin->FirstStage != ~0U; ++itin) {
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const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
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allStage1Units |= IS->getUnits();
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}
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InstrItins.IssueWidth = 0;
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while (allStage1Units) {
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++InstrItins.IssueWidth;
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// clear the lowest bit
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allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
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}
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2011-01-04 08:32:57 +08:00
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assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 13:03:26 +08:00
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}
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2009-11-10 08:48:55 +08:00
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bool ARMSubtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtarget::AntiDepBreakMode& Mode,
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2009-11-14 03:52:48 +08:00
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RegClassVector& CriticalPathRCs) const {
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2009-11-10 08:48:55 +08:00
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Mode = TargetSubtarget::ANTIDEP_CRITICAL;
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2009-11-14 03:52:48 +08:00
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(&ARM::GPRRegClass);
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2009-11-10 08:48:55 +08:00
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return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
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}
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