llvm-project/llvm/test/CodeGen/AMDGPU/gws-hazards.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=VI %s
# RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=CI %s
# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=SI %s

---
name: m0_gws_init0
tracksRegLiveness: true
body: |

  bb.0:
    liveins: $vgpr0
    ; GFX9-LABEL: name: m0_gws_init0
    ; GFX9: liveins: $vgpr0
    ; GFX9: $m0 = S_MOV_B32 -1
    ; GFX9: S_NOP 0
    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; VI-LABEL: name: m0_gws_init0
    ; VI: liveins: $vgpr0
    ; VI: $m0 = S_MOV_B32 -1
    ; VI: S_NOP 0
    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; CI-LABEL: name: m0_gws_init0
    ; CI: liveins: $vgpr0
    ; CI: $m0 = S_MOV_B32 -1
    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; SI-LABEL: name: m0_gws_init0
    ; SI: liveins: $vgpr0
    ; SI: $m0 = S_MOV_B32 -1
    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    $m0 = S_MOV_B32 -1
    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec

...

---
name: m0_gws_init1
tracksRegLiveness: true
body: |

  bb.0:
    ; GFX9-LABEL: name: m0_gws_init1
    ; GFX9: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    ; GFX9: $m0 = S_MOV_B32 -1
    ; GFX9: S_NOP 0
    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; VI-LABEL: name: m0_gws_init1
    ; VI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    ; VI: $m0 = S_MOV_B32 -1
    ; VI: S_NOP 0
    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; CI-LABEL: name: m0_gws_init1
    ; CI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    ; CI: $m0 = S_MOV_B32 -1
    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; SI-LABEL: name: m0_gws_init1
    ; SI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    ; SI: $m0 = S_MOV_B32 -1
    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    $vgpr0  = V_MOV_B32_e32 0, implicit $exec
    $m0 = S_MOV_B32 -1
    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec

...

# Test a typical situation where m0 needs to be set from a VGPR
# through readfirstlane
---
name: m0_gws_readlane
tracksRegLiveness: true
body: |

  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX9-LABEL: name: m0_gws_readlane
    ; GFX9: liveins: $vgpr0, $vgpr1
    ; GFX9: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
    ; GFX9: $m0 = S_MOV_B32 $sgpr0
    ; GFX9: S_NOP 0
    ; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; VI-LABEL: name: m0_gws_readlane
    ; VI: liveins: $vgpr0, $vgpr1
    ; VI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
    ; VI: $m0 = S_MOV_B32 $sgpr0
    ; VI: S_NOP 0
    ; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; CI-LABEL: name: m0_gws_readlane
    ; CI: liveins: $vgpr0, $vgpr1
    ; CI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
    ; CI: $m0 = S_MOV_B32 $sgpr0
    ; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    ; SI-LABEL: name: m0_gws_readlane
    ; SI: liveins: $vgpr0, $vgpr1
    ; SI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
    ; SI: $m0 = S_MOV_B32 $sgpr0
    ; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
    $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
    $m0 = S_MOV_B32 $sgpr0
    DS_GWS_INIT  $vgpr0, 0, 1, implicit $m0, implicit $exec

...