[AMDGPU] Check MI bundles for hazards
Summary: GCNHazardRecognizer fails to identify hazards that are in and around bundles. This patch allows the hazard recognizer to consider bundled instructions in both scheduler and hazard recognizer mode. We ignore “bundledness” for the purpose of detecting hazards and examine the instructions individually.
Reviewers: arsenm, msearles, rampitec
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61564
llvm-svn: 360199
2019-05-08 06:12:15 +08:00
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# RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK,GCX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX9 %s
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2019-06-13 02:44:11 +08:00
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX10 %s
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[AMDGPU] Check MI bundles for hazards
Summary: GCNHazardRecognizer fails to identify hazards that are in and around bundles. This patch allows the hazard recognizer to consider bundled instructions in both scheduler and hazard recognizer mode. We ignore “bundledness” for the purpose of detecting hazards and examine the instructions individually.
Reviewers: arsenm, msearles, rampitec
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61564
llvm-svn: 360199
2019-05-08 06:12:15 +08:00
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# GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr_hidden_bundle
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[AMDGPU] Enable serializing of argument info.
Summary:
- Support serialization of all arguments in machine function info. This
enables fabricating MIR tests depending on argument info.
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64096
llvm-svn: 364995
2019-07-03 10:00:21 +08:00
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# GCN: bb.0:
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[AMDGPU] Check MI bundles for hazards
Summary: GCNHazardRecognizer fails to identify hazards that are in and around bundles. This patch allows the hazard recognizer to consider bundled instructions in both scheduler and hazard recognizer mode. We ignore “bundledness” for the purpose of detecting hazards and examine the instructions individually.
Reviewers: arsenm, msearles, rampitec
Reviewed By: rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61564
llvm-svn: 360199
2019-05-08 06:12:15 +08:00
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# GCN: }
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# XNACK-NEXT: S_NOP
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# NOXNACK-NOT: S_NOP
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# GCN: S_LOAD_DWORDX2_IMM
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---
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name: break_smem_clause_simple_load_smrd8_ptr_hidden_bundle
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body: |
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bb.0:
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BUNDLE implicit-def $sgpr6_sgpr7 {
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$sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0, 0
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}
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$sgpr14_sgpr15 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
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S_ENDPGM 0
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...
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# GFX9-LABEL: name: hazard_precedes_bundle
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# GFX9: S_MOV_B32
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# GFX9-NEXT: S_NOP
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# GFX9: BUNDLE
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# GFX9-NEXT: S_NOP
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---
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name: hazard_precedes_bundle
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body: |
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bb.0:
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$m0 = S_MOV_B32 $sgpr7
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S_SENDMSG 3, implicit $exec, implicit $m0
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$m0 = S_MOV_B32 $sgpr8
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BUNDLE implicit-def $vgpr0 {
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$vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $m0, implicit $exec
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}
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S_ENDPGM 0
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...
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# GCN-LABEL: name: vmem_vcc_hazard_ignore_bundle_instr
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# GCN: S_LOAD_DWORDX2_IMM
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# GCN-NEXT: }
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_hazard_ignore_bundle_instr
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body: |
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bb.0:
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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BUNDLE implicit-def $vgpr1, implicit $vgpr0, implicit $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec {
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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}
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BUNDLE implicit-def $sgpr0_sgpr1, implicit $sgpr10_sgpr11 {
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$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
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}
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two_after_bundle
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# GCN: bb.2:
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: S_NOP
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two_after_bundle
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body: |
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bb.0:
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successors: %bb.2
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BUNDLE implicit-def $vgpr1, implicit $vgpr0 {
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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}
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S_NOP 0
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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BUNDLE implicit-def $vgpr1, implicit $vgpr0 {
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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}
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bb.2:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
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...
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