forked from OSchip/llvm-project
48 lines
1.3 KiB
Plaintext
48 lines
1.3 KiB
Plaintext
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{
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"arrays" : [
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{
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"name" : "MemRef_tmp",
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"sizes" : [ "*" ],
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"type" : "double"
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}
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],
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"context" : "{ : }",
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"name" : "%bb2---%bb14",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb2[i0] -> MemRef_tmp[i0] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb2[i0] -> MemRef_tmp[i0] }"
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}
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],
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"domain" : "{ Stmt_bb2[i0] : 0 <= i0 <= 1199 }",
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"name" : "Stmt_bb2",
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"schedule" : "{ Stmt_bb2[i0] -> [i0, 0, 0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb6[i0, i1] -> MemRef_tmp[i0] : i1 <= 898 }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb6[i0, i1] -> MemRef_tmp[i0] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb6[i0, i1] -> MemRef_tmp[i0] }"
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}
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],
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"domain" : "{ Stmt_bb6[i0, i1] : 0 <= i0 <= 1199 and 0 <= i1 <= 899 }",
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"name" : "Stmt_bb6",
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"schedule" : "{ Stmt_bb6[i0, i1] -> [i0, 1, i1] }"
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}
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]
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}
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