2010-08-10 07:59:04 +08:00
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//===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
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2010-01-13 08:30:23 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2010-01-13 15:59:13 +08:00
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//
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2010-08-10 07:59:04 +08:00
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// Perform peephole optimizations on the machine code:
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2010-01-13 15:59:13 +08:00
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//
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2010-08-10 07:59:04 +08:00
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// - Optimize Extensions
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2010-01-13 15:59:13 +08:00
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//
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2010-08-10 07:59:04 +08:00
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// Optimization of sign / zero extension instructions. It may be extended to
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// handle other instructions with similar properties.
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//
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// On some targets, some instructions, e.g. X86 sign / zero extension, may
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// leave the source value in the lower part of the result. This optimization
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// will replace some uses of the pre-extension value with uses of the
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// sub-register of the results.
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//
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// - Optimize Comparisons
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//
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// Optimization of comparison instructions. For instance, in this code:
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//
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// sub r1, 1
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// cmp r1, 0
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// bz L1
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//
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// If the "sub" instruction all ready sets (or could be modified to set) the
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// same flag that the "cmp" instruction sets and that "bz" uses, then we can
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// eliminate the "cmp" instruction.
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2012-05-11 09:30:47 +08:00
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//
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// Another instance, in this code:
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//
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// sub r1, r3 | sub r1, imm
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// cmp r3, r1 or cmp r1, r3 | cmp r1, imm
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// bge L1
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//
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// If the branch instruction can use flag from "sub", then we can replace
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// "sub" with "subs" and eliminate the "cmp" instruction.
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2011-03-15 13:13:13 +08:00
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//
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2012-12-12 00:10:25 +08:00
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// - Optimize Loads:
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//
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// Loads that can be folded into a later instruction. A load is foldable
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// if it loads to virtual registers and the virtual register defined has
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// a single use.
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2013-09-14 02:26:31 +08:00
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//
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[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
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// - Optimize Copies and Bitcast (more generally, target specific copies):
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2013-09-14 02:26:31 +08:00
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//
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// Rewrite copies and bitcasts to avoid cross register bank copies
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// when possible.
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// E.g., Consider the following example, where capital and lower
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// letters denote different register file:
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// b = copy A <-- cross-bank copy
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// C = copy b <-- cross-bank copy
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// =>
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// b = copy A <-- cross-bank copy
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// C = copy A <-- same-bank copy
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//
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// E.g., for bitcast:
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// b = bitcast A <-- cross-bank copy
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// C = bitcast b <-- cross-bank copy
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// =>
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// b = bitcast A <-- cross-bank copy
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// C = copy A <-- same-bank copy
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2010-01-13 15:59:13 +08:00
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//===----------------------------------------------------------------------===//
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2010-01-13 08:30:23 +08:00
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#include "llvm/CodeGen/Passes.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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2010-01-13 08:30:23 +08:00
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Support/CommandLine.h"
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2012-12-17 11:56:00 +08:00
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#include "llvm/Support/Debug.h"
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2015-03-24 03:32:43 +08:00
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#include "llvm/Support/raw_ostream.h"
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2010-01-13 08:30:23 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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2014-08-05 05:25:23 +08:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
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#include <utility>
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2010-01-13 08:30:23 +08:00
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using namespace llvm;
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2014-04-22 10:02:50 +08:00
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#define DEBUG_TYPE "peephole-opt"
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2010-08-10 07:59:04 +08:00
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// Optimize Extensions
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static cl::opt<bool>
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Aggressive("aggressive-ext-opt", cl::Hidden,
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cl::desc("Aggressive extension optimization"));
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2010-01-13 08:30:23 +08:00
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When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
llvm-svn: 117950
2010-11-02 04:41:43 +08:00
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static cl::opt<bool>
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DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
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cl::desc("Disable the peephole optimizer"));
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[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
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static cl::opt<bool>
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2014-08-22 06:23:52 +08:00
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DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
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[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
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cl::desc("Disable advanced copy optimization"));
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2010-08-28 04:39:09 +08:00
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STATISTIC(NumReuse, "Number of extension results reused");
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2011-03-15 13:13:13 +08:00
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STATISTIC(NumCmps, "Number of compares eliminated");
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2012-02-25 08:46:38 +08:00
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STATISTIC(NumImmFold, "Number of move immediate folded");
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2012-08-02 08:56:42 +08:00
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STATISTIC(NumLoadFold, "Number of loads folded");
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2012-08-17 07:11:47 +08:00
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STATISTIC(NumSelects, "Number of selects optimized");
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[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
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STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
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STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
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2010-08-10 07:59:04 +08:00
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2010-01-13 08:30:23 +08:00
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namespace {
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2010-08-10 07:59:04 +08:00
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class PeepholeOptimizer : public MachineFunctionPass {
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2010-01-13 08:30:23 +08:00
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const TargetInstrInfo *TII;
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2014-10-14 15:17:20 +08:00
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const TargetRegisterInfo *TRI;
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2010-08-10 07:59:04 +08:00
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MachineRegisterInfo *MRI;
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MachineDominatorTree *DT; // Machine dominator tree
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2010-01-13 08:30:23 +08:00
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public:
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static char ID; // Pass identification
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2010-10-20 01:21:58 +08:00
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PeepholeOptimizer() : MachineFunctionPass(ID) {
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initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
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}
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2010-01-13 08:30:23 +08:00
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2014-03-07 17:26:03 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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2010-01-13 08:30:23 +08:00
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2014-03-07 17:26:03 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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2010-01-13 08:30:23 +08:00
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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2010-01-13 15:59:13 +08:00
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if (Aggressive) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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2010-01-13 08:30:23 +08:00
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}
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2010-01-13 15:59:13 +08:00
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private:
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2012-05-02 07:21:41 +08:00
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bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
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bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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2014-08-11 21:52:46 +08:00
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SmallPtrSetImpl<MachineInstr*> &LocalMIs);
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2015-01-13 15:07:13 +08:00
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bool optimizeSelect(MachineInstr *MI,
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SmallPtrSetImpl<MachineInstr *> &LocalMIs);
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[AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.
Examples:
1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
to b.<invCC>
2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
to b.<CC>
rdar://problem/18506500
llvm-svn: 219742
2014-10-15 07:07:53 +08:00
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bool optimizeCondBranch(MachineInstr *MI);
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2013-09-14 02:26:31 +08:00
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bool optimizeCopyOrBitcast(MachineInstr *MI);
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
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bool optimizeCoalescableCopy(MachineInstr *MI);
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bool optimizeUncoalescableCopy(MachineInstr *MI,
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SmallPtrSetImpl<MachineInstr *> &LocalMIs);
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bool findNextSource(unsigned &Reg, unsigned &SubReg);
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2010-11-18 04:13:28 +08:00
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bool isMoveImmediate(MachineInstr *MI,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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2012-05-02 07:21:41 +08:00
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|
|
bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
|
2010-11-18 04:13:28 +08:00
|
|
|
SmallSet<unsigned, 4> &ImmDefRegs,
|
|
|
|
DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
|
2014-04-03 06:59:58 +08:00
|
|
|
bool isLoadFoldable(MachineInstr *MI,
|
|
|
|
SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
|
|
|
|
/// \brief Check whether \p MI is understood by the register coalescer
|
|
|
|
/// but may require some rewriting.
|
|
|
|
bool isCoalescableCopy(const MachineInstr &MI) {
|
|
|
|
// SubregToRegs are not interesting, because they are already register
|
|
|
|
// coalescer friendly.
|
|
|
|
return MI.isCopy() || (!DisableAdvCopyOpt &&
|
|
|
|
(MI.isRegSequence() || MI.isInsertSubreg() ||
|
|
|
|
MI.isExtractSubreg()));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Check whether \p MI is a copy like instruction that is
|
|
|
|
/// not recognized by the register coalescer.
|
|
|
|
bool isUncoalescableCopy(const MachineInstr &MI) {
|
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
advanced copy optimization.
This is the final step patch toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1
and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
into simple generic GPR copies that the coalescer managed to remove.
<rdar://problem/12702965>
llvm-svn: 216144
2014-08-21 08:19:16 +08:00
|
|
|
return MI.isBitcast() ||
|
|
|
|
(!DisableAdvCopyOpt &&
|
|
|
|
(MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
|
|
|
|
MI.isExtractSubregLike()));
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
}
|
2010-01-13 08:30:23 +08:00
|
|
|
};
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
|
|
|
|
/// \brief Helper class to track the possible sources of a value defined by
|
|
|
|
/// a (chain of) copy related instructions.
|
|
|
|
/// Given a definition (instruction and definition index), this class
|
|
|
|
/// follows the use-def chain to find successive suitable sources.
|
|
|
|
/// The given source can be used to rewrite the definition into
|
|
|
|
/// def = COPY src.
|
|
|
|
///
|
|
|
|
/// For instance, let us consider the following snippet:
|
|
|
|
/// v0 =
|
|
|
|
/// v2 = INSERT_SUBREG v1, v0, sub0
|
|
|
|
/// def = COPY v2.sub0
|
|
|
|
///
|
|
|
|
/// Using a ValueTracker for def = COPY v2.sub0 will give the following
|
|
|
|
/// suitable sources:
|
|
|
|
/// v2.sub0 and v0.
|
|
|
|
/// Then, def can be rewritten into def = COPY v0.
|
|
|
|
class ValueTracker {
|
|
|
|
private:
|
|
|
|
/// The current point into the use-def chain.
|
|
|
|
const MachineInstr *Def;
|
|
|
|
/// The index of the definition in Def.
|
|
|
|
unsigned DefIdx;
|
|
|
|
/// The sub register index of the definition.
|
|
|
|
unsigned DefSubReg;
|
|
|
|
/// The register where the value can be found.
|
|
|
|
unsigned Reg;
|
|
|
|
/// Specifiy whether or not the value tracking looks through
|
|
|
|
/// complex instructions. When this is false, the value tracker
|
|
|
|
/// bails on everything that is not a copy or a bitcast.
|
|
|
|
///
|
|
|
|
/// Note: This could have been implemented as a specialized version of
|
|
|
|
/// the ValueTracker class but that would have complicated the code of
|
|
|
|
/// the users of this class.
|
|
|
|
bool UseAdvancedTracking;
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// MachineRegisterInfo used to perform tracking.
|
|
|
|
const MachineRegisterInfo &MRI;
|
|
|
|
/// Optional TargetInstrInfo used to perform some complex
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// tracking.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
const TargetInstrInfo *TII;
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
|
|
|
|
/// \brief Dispatcher to the right underlying implementation of
|
|
|
|
/// getNextSource.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \brief Specialized version of getNextSource for Copy instructions.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool getNextSourceFromCopy(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \brief Specialized version of getNextSource for Bitcast instructions.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool getNextSourceFromBitcast(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \brief Specialized version of getNextSource for RegSequence
|
|
|
|
/// instructions.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool getNextSourceFromRegSequence(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \brief Specialized version of getNextSource for InsertSubreg
|
|
|
|
/// instructions.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool getNextSourceFromInsertSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \brief Specialized version of getNextSource for ExtractSubreg
|
|
|
|
/// instructions.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool getNextSourceFromExtractSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \brief Specialized version of getNextSource for SubregToReg
|
|
|
|
/// instructions.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool getNextSourceFromSubregToReg(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
|
|
|
|
public:
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// \brief Create a ValueTracker instance for the value defined by \p Reg.
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \p DefSubReg represents the sub register index the value tracker will
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// track. It does not need to match the sub register index used in the
|
|
|
|
/// definition of \p Reg.
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \p UseAdvancedTracking specifies whether or not the value tracker looks
|
|
|
|
/// through complex instructions. By default (false), it handles only copy
|
|
|
|
/// and bitcast instructions.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// If \p Reg is a physical register, a value tracker constructed with
|
|
|
|
/// this constructor will not find any alternative source.
|
|
|
|
/// Indeed, when \p Reg is a physical register that constructor does not
|
|
|
|
/// know which definition of \p Reg it should track.
|
|
|
|
/// Use the next constructor to track a physical register.
|
|
|
|
ValueTracker(unsigned Reg, unsigned DefSubReg,
|
|
|
|
const MachineRegisterInfo &MRI,
|
|
|
|
bool UseAdvancedTracking = false,
|
|
|
|
const TargetInstrInfo *TII = nullptr)
|
|
|
|
: Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
|
|
|
|
UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
|
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
|
|
Def = MRI.getVRegDef(Reg);
|
|
|
|
DefIdx = MRI.def_begin(Reg).getOperandNo();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Create a ValueTracker instance for the value defined by
|
|
|
|
/// the pair \p MI, \p DefIdx.
|
|
|
|
/// Unlike the other constructor, the value tracker produced by this one
|
|
|
|
/// may be able to find a new source when the definition is a physical
|
|
|
|
/// register.
|
|
|
|
/// This could be useful to rewrite target specific instructions into
|
|
|
|
/// generic copy instructions.
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
const MachineRegisterInfo &MRI,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
bool UseAdvancedTracking = false,
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
const TargetInstrInfo *TII = nullptr)
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
: Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
|
|
|
|
assert(DefIdx < Def->getDesc().getNumDefs() &&
|
|
|
|
Def->getOperand(DefIdx).isReg() && "Invalid definition");
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
Reg = Def->getOperand(DefIdx).getReg();
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Following the use-def chain, get the next available source
|
|
|
|
/// for the tracked value.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// When the returned value is not nullptr, \p SrcReg gives the register
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// that contain the tracked value.
|
|
|
|
/// \note The sub register index returned in \p SrcSubReg must be used
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// on \p SrcReg to access the actual value.
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
/// \return Unless the returned value is nullptr (i.e., no source found),
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// \p SrcReg gives the register of the next source used in the returned
|
|
|
|
/// instruction and \p SrcSubReg the sub-register index to be used on that
|
|
|
|
/// source to get the tracked value. When nullptr is returned, no
|
|
|
|
/// alternative source has been found.
|
|
|
|
const MachineInstr *getNextSource(unsigned &SrcReg, unsigned &SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
|
|
|
|
/// \brief Get the last register where the initial value can be found.
|
|
|
|
/// Initially this is the register of the definition.
|
|
|
|
/// Then, after each successful call to getNextSource, this is the
|
|
|
|
/// register of the last source.
|
|
|
|
unsigned getReg() const { return Reg; }
|
|
|
|
};
|
2015-06-19 23:57:42 +08:00
|
|
|
} // namespace
|
2010-01-13 08:30:23 +08:00
|
|
|
|
2010-08-10 07:59:04 +08:00
|
|
|
char PeepholeOptimizer::ID = 0;
|
2012-02-09 05:23:13 +08:00
|
|
|
char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
|
2010-10-13 03:48:12 +08:00
|
|
|
INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
|
|
|
|
"Peephole Optimizations", false, false)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
|
|
|
|
INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
|
2010-10-08 06:25:06 +08:00
|
|
|
"Peephole Optimizations", false, false)
|
2010-08-10 07:59:04 +08:00
|
|
|
|
2012-05-02 07:21:41 +08:00
|
|
|
/// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
|
2010-08-10 07:59:04 +08:00
|
|
|
/// a single register and writes a single register and it does not modify the
|
|
|
|
/// source, and if the source value is preserved as a sub-register of the
|
|
|
|
/// result, then replace all reachable uses of the source with the subreg of the
|
|
|
|
/// result.
|
2012-02-09 05:22:43 +08:00
|
|
|
///
|
2010-08-10 07:59:04 +08:00
|
|
|
/// Do not generate an EXTRACT that is used only in a debug use, as this changes
|
|
|
|
/// the code. Since this code does not currently share EXTRACTs, just ignore all
|
|
|
|
/// debug uses.
|
|
|
|
bool PeepholeOptimizer::
|
2012-05-02 07:21:41 +08:00
|
|
|
optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
|
2014-08-11 21:52:46 +08:00
|
|
|
SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
|
2010-01-13 15:59:13 +08:00
|
|
|
unsigned SrcReg, DstReg, SubIdx;
|
2010-08-03 06:06:08 +08:00
|
|
|
if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
|
|
|
|
return false;
|
2012-02-09 05:22:43 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
|
|
|
|
TargetRegisterInfo::isPhysicalRegister(SrcReg))
|
|
|
|
return false;
|
|
|
|
|
2012-06-20 05:10:18 +08:00
|
|
|
if (MRI->hasOneNonDBGUse(SrcReg))
|
2010-08-03 06:06:08 +08:00
|
|
|
// No other uses.
|
|
|
|
return false;
|
|
|
|
|
2012-05-21 02:42:55 +08:00
|
|
|
// Ensure DstReg can get a register class that actually supports
|
|
|
|
// sub-registers. Don't change the class until we commit.
|
|
|
|
const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
|
2014-10-14 15:17:20 +08:00
|
|
|
DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
|
2012-05-21 02:42:55 +08:00
|
|
|
if (!DstRC)
|
|
|
|
return false;
|
|
|
|
|
2012-06-20 05:14:34 +08:00
|
|
|
// The ext instr may be operating on a sub-register of SrcReg as well.
|
|
|
|
// PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
|
|
|
|
// register.
|
|
|
|
// If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
|
|
|
|
// SrcReg:SubIdx should be replaced.
|
2014-08-05 05:25:23 +08:00
|
|
|
bool UseSrcSubIdx =
|
2014-10-14 15:17:20 +08:00
|
|
|
TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
|
2012-06-20 05:14:34 +08:00
|
|
|
|
2010-08-10 07:59:04 +08:00
|
|
|
// The source has other uses. See if we can replace the other uses with use of
|
|
|
|
// the result of the extension.
|
2010-08-03 06:06:08 +08:00
|
|
|
SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
|
2014-03-18 03:36:09 +08:00
|
|
|
for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
|
|
|
|
ReachedBBs.insert(UI.getParent());
|
2010-08-03 06:06:08 +08:00
|
|
|
|
|
|
|
// Uses that are in the same BB of uses of the result of the instruction.
|
|
|
|
SmallVector<MachineOperand*, 8> Uses;
|
2010-08-10 07:59:04 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
// Uses that the result of the instruction can reach.
|
|
|
|
SmallVector<MachineOperand*, 8> ExtendedUses;
|
|
|
|
|
2010-08-10 07:59:04 +08:00
|
|
|
bool ExtendLife = true;
|
2014-03-18 03:36:09 +08:00
|
|
|
for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
|
2014-03-14 07:12:04 +08:00
|
|
|
MachineInstr *UseMI = UseMO.getParent();
|
2010-08-03 06:06:08 +08:00
|
|
|
if (UseMI == MI)
|
|
|
|
continue;
|
2010-08-10 07:59:04 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
if (UseMI->isPHI()) {
|
|
|
|
ExtendLife = false;
|
|
|
|
continue;
|
|
|
|
}
|
2010-01-13 15:59:13 +08:00
|
|
|
|
2012-06-20 05:14:34 +08:00
|
|
|
// Only accept uses of SrcReg:SubIdx.
|
|
|
|
if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
|
|
|
|
continue;
|
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
// It's an error to translate this:
|
|
|
|
//
|
|
|
|
// %reg1025 = <sext> %reg1024
|
|
|
|
// ...
|
|
|
|
// %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
|
|
|
|
//
|
|
|
|
// into this:
|
|
|
|
//
|
|
|
|
// %reg1025 = <sext> %reg1024
|
|
|
|
// ...
|
|
|
|
// %reg1027 = COPY %reg1025:4
|
|
|
|
// %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
|
|
|
|
//
|
|
|
|
// The problem here is that SUBREG_TO_REG is there to assert that an
|
|
|
|
// implicit zext occurs. It doesn't insert a zext instruction. If we allow
|
|
|
|
// the COPY here, it will give us the value after the <sext>, not the
|
|
|
|
// original value of %reg1024 before <sext>.
|
|
|
|
if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
MachineBasicBlock *UseMBB = UseMI->getParent();
|
|
|
|
if (UseMBB == MBB) {
|
|
|
|
// Local uses that come after the extension.
|
|
|
|
if (!LocalMIs.count(UseMI))
|
|
|
|
Uses.push_back(&UseMO);
|
2010-08-10 07:59:04 +08:00
|
|
|
} else if (ReachedBBs.count(UseMBB)) {
|
|
|
|
// Non-local uses where the result of the extension is used. Always
|
|
|
|
// replace these unless it's a PHI.
|
2010-08-03 06:06:08 +08:00
|
|
|
Uses.push_back(&UseMO);
|
2010-08-10 07:59:04 +08:00
|
|
|
} else if (Aggressive && DT->dominates(MBB, UseMBB)) {
|
|
|
|
// We may want to extend the live range of the extension result in order
|
|
|
|
// to replace these uses.
|
2010-08-03 06:06:08 +08:00
|
|
|
ExtendedUses.push_back(&UseMO);
|
2010-08-10 07:59:04 +08:00
|
|
|
} else {
|
2010-08-03 06:06:08 +08:00
|
|
|
// Both will be live out of the def MBB anyway. Don't extend live range of
|
|
|
|
// the extension result.
|
|
|
|
ExtendLife = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2010-01-13 15:59:13 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
if (ExtendLife && !ExtendedUses.empty())
|
2010-08-10 07:59:04 +08:00
|
|
|
// Extend the liveness of the extension result.
|
2015-02-28 18:11:12 +08:00
|
|
|
Uses.append(ExtendedUses.begin(), ExtendedUses.end());
|
2010-01-14 03:16:39 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
// Now replace all uses.
|
|
|
|
bool Changed = false;
|
|
|
|
if (!Uses.empty()) {
|
|
|
|
SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
|
2010-08-10 07:59:04 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
// Look for PHI uses of the extended result, we don't want to extend the
|
|
|
|
// liveness of a PHI input. It breaks all kinds of assumptions down
|
|
|
|
// stream. A PHI use is expected to be the kill of its source values.
|
2014-03-18 03:36:09 +08:00
|
|
|
for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
|
|
|
|
if (UI.isPHI())
|
|
|
|
PHIBBs.insert(UI.getParent());
|
2010-06-10 03:00:55 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
|
|
|
|
for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
|
|
|
|
MachineOperand *UseMO = Uses[i];
|
|
|
|
MachineInstr *UseMI = UseMO->getParent();
|
2010-01-13 15:59:13 +08:00
|
|
|
MachineBasicBlock *UseMBB = UseMI->getParent();
|
2010-08-03 06:06:08 +08:00
|
|
|
if (PHIBBs.count(UseMBB))
|
|
|
|
continue;
|
2010-08-10 07:59:04 +08:00
|
|
|
|
2012-02-25 10:01:00 +08:00
|
|
|
// About to add uses of DstReg, clear DstReg's kill flags.
|
2012-05-21 02:42:55 +08:00
|
|
|
if (!Changed) {
|
2012-02-25 10:01:00 +08:00
|
|
|
MRI->clearKillFlags(DstReg);
|
2012-05-21 02:42:55 +08:00
|
|
|
MRI->constrainRegClass(DstReg, DstRC);
|
|
|
|
}
|
2012-02-25 10:01:00 +08:00
|
|
|
|
2010-08-03 06:06:08 +08:00
|
|
|
unsigned NewVR = MRI->createVirtualRegister(RC);
|
2012-06-20 05:14:34 +08:00
|
|
|
MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
|
|
|
|
TII->get(TargetOpcode::COPY), NewVR)
|
2010-08-03 06:06:08 +08:00
|
|
|
.addReg(DstReg, 0, SubIdx);
|
2012-06-20 05:14:34 +08:00
|
|
|
// SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
|
|
|
|
if (UseSrcSubIdx) {
|
|
|
|
Copy->getOperand(0).setSubReg(SubIdx);
|
|
|
|
Copy->getOperand(0).setIsUndef();
|
|
|
|
}
|
2010-08-03 06:06:08 +08:00
|
|
|
UseMO->setReg(NewVR);
|
|
|
|
++NumReuse;
|
|
|
|
Changed = true;
|
2010-01-13 15:59:13 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
2012-05-02 07:21:41 +08:00
|
|
|
/// optimizeCmpInstr - If the instruction is a compare and the previous
|
2010-08-10 07:59:04 +08:00
|
|
|
/// instruction it's comparing against all ready sets (or could be modified to
|
|
|
|
/// set) the same flag as the compare, then we can remove the comparison and use
|
|
|
|
/// the flag from the previous instruction.
|
2012-05-02 07:21:41 +08:00
|
|
|
bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
|
2011-03-15 13:13:13 +08:00
|
|
|
MachineBasicBlock *MBB) {
|
2010-08-10 07:59:04 +08:00
|
|
|
// If this instruction is a comparison against zero and isn't comparing a
|
|
|
|
// physical register, we can try to optimize it.
|
2012-06-30 05:33:59 +08:00
|
|
|
unsigned SrcReg, SrcReg2;
|
2010-09-21 20:01:15 +08:00
|
|
|
int CmpMask, CmpValue;
|
2012-06-30 05:33:59 +08:00
|
|
|
if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
|
|
|
|
TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
|
|
|
|
(SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
|
2010-08-10 07:59:04 +08:00
|
|
|
return false;
|
|
|
|
|
2010-09-11 08:13:50 +08:00
|
|
|
// Attempt to optimize the comparison instruction.
|
2012-06-30 05:33:59 +08:00
|
|
|
if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
|
2011-03-15 13:13:13 +08:00
|
|
|
++NumCmps;
|
2010-08-10 07:59:04 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-08-17 07:11:47 +08:00
|
|
|
/// Optimize a select instruction.
|
2015-01-13 15:07:13 +08:00
|
|
|
bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
|
|
|
|
SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
|
2012-08-17 07:11:47 +08:00
|
|
|
unsigned TrueOp = 0;
|
|
|
|
unsigned FalseOp = 0;
|
|
|
|
bool Optimizable = false;
|
|
|
|
SmallVector<MachineOperand, 4> Cond;
|
|
|
|
if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
|
|
|
|
return false;
|
|
|
|
if (!Optimizable)
|
|
|
|
return false;
|
2015-01-13 15:07:13 +08:00
|
|
|
if (!TII->optimizeSelect(MI, LocalMIs))
|
2012-08-17 07:11:47 +08:00
|
|
|
return false;
|
|
|
|
MI->eraseFromParent();
|
|
|
|
++NumSelects;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
[AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.
Examples:
1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
to b.<invCC>
2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
to b.<CC>
rdar://problem/18506500
llvm-svn: 219742
2014-10-15 07:07:53 +08:00
|
|
|
/// \brief Check if a simpler conditional branch can be
|
|
|
|
// generated
|
|
|
|
bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
|
|
|
|
return TII->optimizeCondBranch(MI);
|
|
|
|
}
|
|
|
|
|
2013-09-14 02:26:31 +08:00
|
|
|
/// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
|
|
|
|
/// share the same register file.
|
|
|
|
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
|
|
|
|
const TargetRegisterClass *DefRC,
|
|
|
|
unsigned DefSubReg,
|
|
|
|
const TargetRegisterClass *SrcRC,
|
|
|
|
unsigned SrcSubReg) {
|
|
|
|
// Same register class.
|
|
|
|
if (DefRC == SrcRC)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Both operands are sub registers. Check if they share a register class.
|
|
|
|
unsigned SrcIdx, DefIdx;
|
|
|
|
if (SrcSubReg && DefSubReg)
|
|
|
|
return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
|
2014-04-14 08:51:57 +08:00
|
|
|
SrcIdx, DefIdx) != nullptr;
|
2013-09-14 02:26:31 +08:00
|
|
|
// At most one of the register is a sub register, make it Src to avoid
|
|
|
|
// duplicating the test.
|
|
|
|
if (!SrcSubReg) {
|
|
|
|
std::swap(DefSubReg, SrcSubReg);
|
|
|
|
std::swap(DefRC, SrcRC);
|
|
|
|
}
|
|
|
|
|
|
|
|
// One of the register is a sub register, check if we can get a superclass.
|
|
|
|
if (SrcSubReg)
|
2014-04-14 08:51:57 +08:00
|
|
|
return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
|
2013-09-14 02:26:31 +08:00
|
|
|
// Plain copy.
|
2014-04-14 08:51:57 +08:00
|
|
|
return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
|
2013-09-14 02:26:31 +08:00
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
/// \brief Try to find the next source that share the same register file
|
|
|
|
/// for the value defined by \p Reg and \p SubReg.
|
|
|
|
/// When true is returned, \p Reg and \p SubReg are updated with the
|
|
|
|
/// register number and sub-register index of the new source.
|
|
|
|
/// \return False if no alternative sources are available. True otherwise.
|
|
|
|
bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) {
|
|
|
|
// Do not try to find a new source for a physical register.
|
|
|
|
// So far we do not have any motivating example for doing that.
|
|
|
|
// Thus, instead of maintaining untested code, we will revisit that if
|
|
|
|
// that changes at some point.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
2013-09-14 02:26:31 +08:00
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
|
|
|
|
unsigned DefSubReg = SubReg;
|
2013-09-14 02:26:31 +08:00
|
|
|
|
|
|
|
unsigned Src;
|
|
|
|
unsigned SrcSubReg;
|
|
|
|
bool ShouldRewrite = false;
|
|
|
|
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// Follow the chain of copies until we reach the top of the use-def chain
|
|
|
|
// or find a more suitable source.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
ValueTracker ValTracker(Reg, DefSubReg, *MRI, !DisableAdvCopyOpt, TII);
|
2013-09-14 02:26:31 +08:00
|
|
|
do {
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
unsigned CopySrcReg, CopySrcSubReg;
|
|
|
|
if (!ValTracker.getNextSource(CopySrcReg, CopySrcSubReg))
|
2013-09-14 02:26:31 +08:00
|
|
|
break;
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
Src = CopySrcReg;
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
SrcSubReg = CopySrcSubReg;
|
|
|
|
|
|
|
|
// Do not extend the live-ranges of physical registers as they add
|
|
|
|
// constraints to the register allocator.
|
|
|
|
// Moreover, if we want to extend the live-range of a physical register,
|
|
|
|
// unlike SSA virtual register, we will have to check that they are not
|
|
|
|
// redefine before the related use.
|
2013-09-14 02:26:31 +08:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Src))
|
|
|
|
break;
|
|
|
|
|
|
|
|
const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
|
|
|
|
|
|
|
|
// If this source does not incur a cross register bank copy, use it.
|
2014-10-14 15:17:20 +08:00
|
|
|
ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, DefSubReg, SrcRC,
|
2013-09-14 02:26:31 +08:00
|
|
|
SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
} while (!ShouldRewrite);
|
2013-09-14 02:26:31 +08:00
|
|
|
|
|
|
|
// If we did not find a more suitable source, there is nothing to optimize.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if (!ShouldRewrite || Src == Reg)
|
2013-09-14 02:26:31 +08:00
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
Reg = Src;
|
|
|
|
SubReg = SrcSubReg;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
/// \brief Helper class to rewrite the arguments of a copy-like instruction.
|
|
|
|
class CopyRewriter {
|
|
|
|
protected:
|
|
|
|
/// The copy-like instruction.
|
|
|
|
MachineInstr &CopyLike;
|
|
|
|
/// The index of the source being rewritten.
|
|
|
|
unsigned CurrentSrcIdx;
|
|
|
|
|
|
|
|
public:
|
|
|
|
CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
|
|
|
|
|
|
|
|
virtual ~CopyRewriter() {}
|
|
|
|
|
|
|
|
/// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
|
|
|
|
/// the related value that it affects (TrackReg, TrackSubReg).
|
|
|
|
/// A source is considered rewritable if its register class and the
|
|
|
|
/// register class of the related TrackReg may not be register
|
|
|
|
/// coalescer friendly. In other words, given a copy-like instruction
|
|
|
|
/// not all the arguments may be returned at rewritable source, since
|
|
|
|
/// some arguments are none to be register coalescer friendly.
|
|
|
|
///
|
|
|
|
/// Each call of this method moves the current source to the next
|
|
|
|
/// rewritable source.
|
|
|
|
/// For instance, let CopyLike be the instruction to rewrite.
|
|
|
|
/// CopyLike has one definition and one source:
|
|
|
|
/// dst.dstSubIdx = CopyLike src.srcSubIdx.
|
|
|
|
///
|
|
|
|
/// The first call will give the first rewritable source, i.e.,
|
|
|
|
/// the only source this instruction has:
|
|
|
|
/// (SrcReg, SrcSubReg) = (src, srcSubIdx).
|
|
|
|
/// This source defines the whole definition, i.e.,
|
|
|
|
/// (TrackReg, TrackSubReg) = (dst, dstSubIdx).
|
|
|
|
///
|
|
|
|
/// The second and subsequent calls will return false, has there is only one
|
|
|
|
/// rewritable source.
|
|
|
|
///
|
|
|
|
/// \return True if a rewritable source has been found, false otherwise.
|
|
|
|
/// The output arguments are valid if and only if true is returned.
|
|
|
|
virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
|
unsigned &TrackReg,
|
|
|
|
unsigned &TrackSubReg) {
|
|
|
|
// If CurrentSrcIdx == 1, this means this function has already been
|
|
|
|
// called once. CopyLike has one defintiion and one argument, thus,
|
|
|
|
// there is nothing else to rewrite.
|
|
|
|
if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
|
|
|
|
return false;
|
|
|
|
// This is the first call to getNextRewritableSource.
|
|
|
|
// Move the CurrentSrcIdx to remember that we made that call.
|
|
|
|
CurrentSrcIdx = 1;
|
|
|
|
// The rewritable source is the argument.
|
|
|
|
const MachineOperand &MOSrc = CopyLike.getOperand(1);
|
|
|
|
SrcReg = MOSrc.getReg();
|
|
|
|
SrcSubReg = MOSrc.getSubReg();
|
|
|
|
// What we track are the alternative sources of the definition.
|
|
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
|
TrackReg = MODef.getReg();
|
|
|
|
TrackSubReg = MODef.getSubReg();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Rewrite the current source with \p NewReg and \p NewSubReg
|
|
|
|
/// if possible.
|
|
|
|
/// \return True if the rewritting was possible, false otherwise.
|
|
|
|
virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
|
|
|
|
if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
|
|
|
|
return false;
|
|
|
|
MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
|
MOSrc.setReg(NewReg);
|
|
|
|
MOSrc.setSubReg(NewSubReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
/// \brief Specialized rewriter for INSERT_SUBREG instruction.
|
|
|
|
class InsertSubregRewriter : public CopyRewriter {
|
|
|
|
public:
|
|
|
|
InsertSubregRewriter(MachineInstr &MI) : CopyRewriter(MI) {
|
|
|
|
assert(MI.isInsertSubreg() && "Invalid instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief See CopyRewriter::getNextRewritableSource.
|
|
|
|
/// Here CopyLike has the following form:
|
|
|
|
/// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
|
|
|
|
/// Src1 has the same register class has dst, hence, there is
|
|
|
|
/// nothing to rewrite.
|
|
|
|
/// Src2.src2SubIdx, may not be register coalescer friendly.
|
|
|
|
/// Therefore, the first call to this method returns:
|
|
|
|
/// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
|
|
|
|
/// (TrackReg, TrackSubReg) = (dst, subIdx).
|
|
|
|
///
|
|
|
|
/// Subsequence calls will return false.
|
|
|
|
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
|
unsigned &TrackReg,
|
|
|
|
unsigned &TrackSubReg) override {
|
|
|
|
// If we already get the only source we can rewrite, return false.
|
|
|
|
if (CurrentSrcIdx == 2)
|
|
|
|
return false;
|
|
|
|
// We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
|
|
|
|
CurrentSrcIdx = 2;
|
|
|
|
const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
|
|
|
|
SrcReg = MOInsertedReg.getReg();
|
|
|
|
SrcSubReg = MOInsertedReg.getSubReg();
|
|
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
|
|
|
|
|
// We want to track something that is compatible with the
|
|
|
|
// partial definition.
|
|
|
|
TrackReg = MODef.getReg();
|
|
|
|
if (MODef.getSubReg())
|
|
|
|
// Bails if we have to compose sub-register indices.
|
|
|
|
return false;
|
|
|
|
TrackSubReg = (unsigned)CopyLike.getOperand(3).getImm();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
|
|
if (CurrentSrcIdx != 2)
|
|
|
|
return false;
|
|
|
|
// We are rewriting the inserted reg.
|
|
|
|
MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
|
MO.setReg(NewReg);
|
|
|
|
MO.setSubReg(NewSubReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
/// \brief Specialized rewriter for EXTRACT_SUBREG instruction.
|
|
|
|
class ExtractSubregRewriter : public CopyRewriter {
|
|
|
|
const TargetInstrInfo &TII;
|
|
|
|
|
|
|
|
public:
|
|
|
|
ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
|
|
|
|
: CopyRewriter(MI), TII(TII) {
|
|
|
|
assert(MI.isExtractSubreg() && "Invalid instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief See CopyRewriter::getNextRewritableSource.
|
|
|
|
/// Here CopyLike has the following form:
|
|
|
|
/// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
|
|
|
|
/// There is only one rewritable source: Src.subIdx,
|
|
|
|
/// which defines dst.dstSubIdx.
|
|
|
|
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
|
unsigned &TrackReg,
|
|
|
|
unsigned &TrackSubReg) override {
|
|
|
|
// If we already get the only source we can rewrite, return false.
|
|
|
|
if (CurrentSrcIdx == 1)
|
|
|
|
return false;
|
|
|
|
// We are looking at v1 = EXTRACT_SUBREG v0, sub0.
|
|
|
|
CurrentSrcIdx = 1;
|
|
|
|
const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
|
|
|
|
SrcReg = MOExtractedReg.getReg();
|
|
|
|
// If we have to compose sub-register indices, bails out.
|
|
|
|
if (MOExtractedReg.getSubReg())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SrcSubReg = CopyLike.getOperand(2).getImm();
|
|
|
|
|
|
|
|
// We want to track something that is compatible with the definition.
|
|
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
|
TrackReg = MODef.getReg();
|
|
|
|
TrackSubReg = MODef.getSubReg();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
|
|
// The only source we can rewrite is the input register.
|
|
|
|
if (CurrentSrcIdx != 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
|
|
|
|
|
|
|
|
// If we find a source that does not require to extract something,
|
|
|
|
// rewrite the operation with a copy.
|
|
|
|
if (!NewSubReg) {
|
|
|
|
// Move the current index to an invalid position.
|
|
|
|
// We do not want another call to this method to be able
|
|
|
|
// to do any change.
|
|
|
|
CurrentSrcIdx = -1;
|
|
|
|
// Rewrite the operation as a COPY.
|
|
|
|
// Get rid of the sub-register index.
|
|
|
|
CopyLike.RemoveOperand(2);
|
|
|
|
// Morph the operation into a COPY.
|
|
|
|
CopyLike.setDesc(TII.get(TargetOpcode::COPY));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
/// \brief Specialized rewriter for REG_SEQUENCE instruction.
|
|
|
|
class RegSequenceRewriter : public CopyRewriter {
|
|
|
|
public:
|
|
|
|
RegSequenceRewriter(MachineInstr &MI) : CopyRewriter(MI) {
|
|
|
|
assert(MI.isRegSequence() && "Invalid instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief See CopyRewriter::getNextRewritableSource.
|
|
|
|
/// Here CopyLike has the following form:
|
|
|
|
/// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
|
|
|
|
/// Each call will return a different source, walking all the available
|
|
|
|
/// source.
|
|
|
|
///
|
|
|
|
/// The first call returns:
|
|
|
|
/// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
|
|
|
|
/// (TrackReg, TrackSubReg) = (dst, subIdx1).
|
|
|
|
///
|
|
|
|
/// The second call returns:
|
|
|
|
/// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
|
|
|
|
/// (TrackReg, TrackSubReg) = (dst, subIdx2).
|
|
|
|
///
|
|
|
|
/// And so on, until all the sources have been traversed, then
|
|
|
|
/// it returns false.
|
|
|
|
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
|
unsigned &TrackReg,
|
|
|
|
unsigned &TrackSubReg) override {
|
|
|
|
// We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
|
|
|
|
|
|
|
|
// If this is the first call, move to the first argument.
|
|
|
|
if (CurrentSrcIdx == 0) {
|
|
|
|
CurrentSrcIdx = 1;
|
|
|
|
} else {
|
|
|
|
// Otherwise, move to the next argument and check that it is valid.
|
|
|
|
CurrentSrcIdx += 2;
|
|
|
|
if (CurrentSrcIdx >= CopyLike.getNumOperands())
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
|
SrcReg = MOInsertedReg.getReg();
|
|
|
|
// If we have to compose sub-register indices, bails out.
|
|
|
|
if ((SrcSubReg = MOInsertedReg.getSubReg()))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// We want to track something that is compatible with the related
|
|
|
|
// partial definition.
|
|
|
|
TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
|
|
|
|
|
|
|
|
const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
|
TrackReg = MODef.getReg();
|
|
|
|
// If we have to compose sub-registers, bails.
|
|
|
|
return MODef.getSubReg() == 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
|
|
// We cannot rewrite out of bound operands.
|
|
|
|
// Moreover, rewritable sources are at odd positions.
|
|
|
|
if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
|
MO.setReg(NewReg);
|
|
|
|
MO.setSubReg(NewSubReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
} // End namespace.
|
|
|
|
|
|
|
|
/// \brief Get the appropriated CopyRewriter for \p MI.
|
|
|
|
/// \return A pointer to a dynamically allocated CopyRewriter or nullptr
|
|
|
|
/// if no rewriter works for \p MI.
|
|
|
|
static CopyRewriter *getCopyRewriter(MachineInstr &MI,
|
|
|
|
const TargetInstrInfo &TII) {
|
|
|
|
switch (MI.getOpcode()) {
|
|
|
|
default:
|
|
|
|
return nullptr;
|
|
|
|
case TargetOpcode::COPY:
|
|
|
|
return new CopyRewriter(MI);
|
|
|
|
case TargetOpcode::INSERT_SUBREG:
|
|
|
|
return new InsertSubregRewriter(MI);
|
|
|
|
case TargetOpcode::EXTRACT_SUBREG:
|
|
|
|
return new ExtractSubregRewriter(MI, TII);
|
|
|
|
case TargetOpcode::REG_SEQUENCE:
|
|
|
|
return new RegSequenceRewriter(MI);
|
|
|
|
}
|
|
|
|
llvm_unreachable(nullptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Optimize generic copy instructions to avoid cross
|
|
|
|
/// register bank copy. The optimization looks through a chain of
|
|
|
|
/// copies and tries to find a source that has a compatible register
|
|
|
|
/// class.
|
|
|
|
/// Two register classes are considered to be compatible if they share
|
|
|
|
/// the same register bank.
|
|
|
|
/// New copies issued by this optimization are register allocator
|
|
|
|
/// friendly. This optimization does not remove any copy as it may
|
|
|
|
/// overconstraint the register allocator, but replaces some operands
|
|
|
|
/// when possible.
|
|
|
|
/// \pre isCoalescableCopy(*MI) is true.
|
|
|
|
/// \return True, when \p MI has been rewritten. False otherwise.
|
|
|
|
bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
|
|
|
|
assert(MI && isCoalescableCopy(*MI) && "Invalid argument");
|
|
|
|
assert(MI->getDesc().getNumDefs() == 1 &&
|
|
|
|
"Coalescer can understand multiple defs?!");
|
|
|
|
const MachineOperand &MODef = MI->getOperand(0);
|
|
|
|
// Do not rewrite physical definitions.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
bool Changed = false;
|
|
|
|
// Get the right rewriter for the current copy.
|
|
|
|
std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII));
|
|
|
|
// If none exists, bails out.
|
|
|
|
if (!CpyRewriter)
|
|
|
|
return false;
|
|
|
|
// Rewrite each rewritable source.
|
|
|
|
unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
|
|
|
|
while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
|
|
|
|
TrackSubReg)) {
|
|
|
|
unsigned NewSrc = TrackReg;
|
|
|
|
unsigned NewSubReg = TrackSubReg;
|
|
|
|
// Try to find a more suitable source.
|
|
|
|
// If we failed to do so, or get the actual source,
|
|
|
|
// move to the next source.
|
|
|
|
if (!findNextSource(NewSrc, NewSubReg) || SrcReg == NewSrc)
|
|
|
|
continue;
|
|
|
|
// Rewrite source.
|
2014-08-22 05:34:06 +08:00
|
|
|
if (CpyRewriter->RewriteCurrentSource(NewSrc, NewSubReg)) {
|
|
|
|
// We may have extended the live-range of NewSrc, account for that.
|
|
|
|
MRI->clearKillFlags(NewSrc);
|
|
|
|
Changed = true;
|
|
|
|
}
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
}
|
|
|
|
// TODO: We could have a clean-up method to tidy the instruction.
|
|
|
|
// E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
|
|
|
|
// => v0 = COPY v1
|
|
|
|
// Currently we haven't seen motivating example for that and we
|
|
|
|
// want to avoid untested code.
|
2015-03-09 09:57:13 +08:00
|
|
|
NumRewrittenCopies += Changed;
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Optimize copy-like instructions to create
|
|
|
|
/// register coalescer friendly instruction.
|
|
|
|
/// The optimization tries to kill-off the \p MI by looking
|
|
|
|
/// through a chain of copies to find a source that has a compatible
|
|
|
|
/// register class.
|
|
|
|
/// If such a source is found, it replace \p MI by a generic COPY
|
|
|
|
/// operation.
|
|
|
|
/// \pre isUncoalescableCopy(*MI) is true.
|
|
|
|
/// \return True, when \p MI has been optimized. In that case, \p MI has
|
|
|
|
/// been removed from its parent.
|
|
|
|
/// All COPY instructions created, are inserted in \p LocalMIs.
|
|
|
|
bool PeepholeOptimizer::optimizeUncoalescableCopy(
|
|
|
|
MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
|
|
|
|
assert(MI && isUncoalescableCopy(*MI) && "Invalid argument");
|
|
|
|
|
|
|
|
// Check if we can rewrite all the values defined by this instruction.
|
|
|
|
SmallVector<
|
|
|
|
std::pair<TargetInstrInfo::RegSubRegPair, TargetInstrInfo::RegSubRegPair>,
|
|
|
|
4> RewritePairs;
|
|
|
|
for (const MachineOperand &MODef : MI->defs()) {
|
|
|
|
if (MODef.isDead())
|
|
|
|
// We can ignore those.
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// If a physical register is here, this is probably for a good reason.
|
|
|
|
// Do not rewrite that.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If we do not know how to rewrite this definition, there is no point
|
|
|
|
// in trying to kill this instruction.
|
|
|
|
TargetInstrInfo::RegSubRegPair Def(MODef.getReg(), MODef.getSubReg());
|
|
|
|
TargetInstrInfo::RegSubRegPair Src = Def;
|
|
|
|
if (!findNextSource(Src.Reg, Src.SubReg))
|
|
|
|
return false;
|
|
|
|
RewritePairs.push_back(std::make_pair(Def, Src));
|
|
|
|
}
|
|
|
|
// The change is possible for all defs, do it.
|
|
|
|
for (const auto &PairDefSrc : RewritePairs) {
|
|
|
|
const auto &Def = PairDefSrc.first;
|
|
|
|
const auto &Src = PairDefSrc.second;
|
|
|
|
// Rewrite the "copy" in a way the register coalescer understands.
|
|
|
|
assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
|
|
|
|
"We do not rewrite physical registers");
|
|
|
|
const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
|
|
|
|
unsigned NewVR = MRI->createVirtualRegister(DefRC);
|
|
|
|
MachineInstr *NewCopy = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
|
|
TII->get(TargetOpcode::COPY),
|
|
|
|
NewVR).addReg(Src.Reg, 0, Src.SubReg);
|
|
|
|
NewCopy->getOperand(0).setSubReg(Def.SubReg);
|
|
|
|
if (Def.SubReg)
|
|
|
|
NewCopy->getOperand(0).setIsUndef();
|
|
|
|
LocalMIs.insert(NewCopy);
|
|
|
|
MRI->replaceRegWith(Def.Reg, NewVR);
|
|
|
|
MRI->clearKillFlags(NewVR);
|
|
|
|
// We extended the lifetime of Src.
|
|
|
|
// Clear the kill flags to account for that.
|
|
|
|
MRI->clearKillFlags(Src.Reg);
|
|
|
|
}
|
|
|
|
// MI is now dead.
|
2013-09-14 02:26:31 +08:00
|
|
|
MI->eraseFromParent();
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
++NumUncoalescableCopies;
|
2013-09-14 02:26:31 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-08-02 08:56:42 +08:00
|
|
|
/// isLoadFoldable - Check whether MI is a candidate for folding into a later
|
|
|
|
/// instruction. We only fold loads to virtual registers and the virtual
|
|
|
|
/// register defined has a single use.
|
2014-04-03 06:59:58 +08:00
|
|
|
bool PeepholeOptimizer::isLoadFoldable(
|
|
|
|
MachineInstr *MI,
|
|
|
|
SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
|
2012-08-03 03:37:32 +08:00
|
|
|
if (!MI->canFoldAsLoad() || !MI->mayLoad())
|
|
|
|
return false;
|
|
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
|
|
if (MCID.getNumDefs() != 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
2014-03-14 02:47:12 +08:00
|
|
|
// To reduce compilation time, we check MRI->hasOneNonDBGUse when inserting
|
2012-08-03 03:37:32 +08:00
|
|
|
// loads. It should be checked when processing uses of the load, since
|
|
|
|
// uses can be removed during peephole.
|
|
|
|
if (!MI->getOperand(0).getSubReg() &&
|
|
|
|
TargetRegisterInfo::isVirtualRegister(Reg) &&
|
2014-03-14 02:47:12 +08:00
|
|
|
MRI->hasOneNonDBGUse(Reg)) {
|
2014-04-03 06:59:58 +08:00
|
|
|
FoldAsLoadDefCandidates.insert(Reg);
|
2012-08-03 03:37:32 +08:00
|
|
|
return true;
|
2012-08-02 08:56:42 +08:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-11-18 04:13:28 +08:00
|
|
|
bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
|
|
|
|
SmallSet<unsigned, 4> &ImmDefRegs,
|
|
|
|
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
2011-06-29 03:10:37 +08:00
|
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
2011-12-07 15:15:52 +08:00
|
|
|
if (!MI->isMoveImmediate())
|
2010-11-18 04:13:28 +08:00
|
|
|
return false;
|
2011-06-29 03:10:37 +08:00
|
|
|
if (MCID.getNumDefs() != 1)
|
2010-11-18 04:13:28 +08:00
|
|
|
return false;
|
|
|
|
unsigned Reg = MI->getOperand(0).getReg();
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
|
|
ImmDefMIs.insert(std::make_pair(Reg, MI));
|
|
|
|
ImmDefRegs.insert(Reg);
|
|
|
|
return true;
|
|
|
|
}
|
2012-02-09 05:22:43 +08:00
|
|
|
|
2010-11-18 04:13:28 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-05-02 07:21:41 +08:00
|
|
|
/// foldImmediate - Try folding register operands that are defined by move
|
2010-11-18 04:13:28 +08:00
|
|
|
/// immediate instructions, i.e. a trivial constant folding optimization, if
|
|
|
|
/// and only if the def and use are in the same BB.
|
2012-05-02 07:21:41 +08:00
|
|
|
bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
|
2010-11-18 04:13:28 +08:00
|
|
|
SmallSet<unsigned, 4> &ImmDefRegs,
|
|
|
|
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
|
|
|
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg() || MO.isDef())
|
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
2011-01-10 10:58:51 +08:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
2010-11-18 04:13:28 +08:00
|
|
|
continue;
|
|
|
|
if (ImmDefRegs.count(Reg) == 0)
|
|
|
|
continue;
|
|
|
|
DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
|
|
|
|
assert(II != ImmDefMIs.end());
|
|
|
|
if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
|
|
|
|
++NumImmFold;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-10-16 05:06:25 +08:00
|
|
|
bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
if (skipOptnoneFunction(*MF.getFunction()))
|
2014-04-01 01:43:35 +08:00
|
|
|
return false;
|
|
|
|
|
2012-12-17 11:56:00 +08:00
|
|
|
DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
|
2014-10-16 05:06:25 +08:00
|
|
|
DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
|
2012-12-17 11:56:00 +08:00
|
|
|
|
2010-11-16 05:20:45 +08:00
|
|
|
if (DisablePeephole)
|
|
|
|
return false;
|
2012-02-09 05:22:43 +08:00
|
|
|
|
2014-10-16 05:06:25 +08:00
|
|
|
TII = MF.getSubtarget().getInstrInfo();
|
|
|
|
TRI = MF.getSubtarget().getRegisterInfo();
|
|
|
|
MRI = &MF.getRegInfo();
|
2014-04-14 08:51:57 +08:00
|
|
|
DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
|
2010-01-13 08:30:23 +08:00
|
|
|
|
|
|
|
bool Changed = false;
|
|
|
|
|
2014-10-16 05:06:25 +08:00
|
|
|
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
|
2010-01-13 08:30:23 +08:00
|
|
|
MachineBasicBlock *MBB = &*I;
|
2012-02-09 05:22:43 +08:00
|
|
|
|
2010-11-18 04:13:28 +08:00
|
|
|
bool SeenMoveImm = false;
|
2015-01-13 15:07:13 +08:00
|
|
|
|
|
|
|
// During this forward scan, at some point it needs to answer the question
|
|
|
|
// "given a pointer to an MI in the current BB, is it located before or
|
|
|
|
// after the current instruction".
|
|
|
|
// To perform this, the following set keeps track of the MIs already seen
|
|
|
|
// during the scan, if a MI is not in the set, it is assumed to be located
|
|
|
|
// after. Newly created MIs have to be inserted in the set as well.
|
2014-08-11 10:50:43 +08:00
|
|
|
SmallPtrSet<MachineInstr*, 16> LocalMIs;
|
2014-04-03 06:59:58 +08:00
|
|
|
SmallSet<unsigned, 4> ImmDefRegs;
|
|
|
|
DenseMap<unsigned, MachineInstr*> ImmDefMIs;
|
|
|
|
SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
|
2010-08-10 07:59:04 +08:00
|
|
|
|
|
|
|
for (MachineBasicBlock::iterator
|
2010-09-11 05:55:43 +08:00
|
|
|
MII = I->begin(), MIE = I->end(); MII != MIE; ) {
|
2011-02-15 05:50:37 +08:00
|
|
|
MachineInstr *MI = &*MII;
|
2012-08-17 22:38:59 +08:00
|
|
|
// We may be erasing MI below, increment MII now.
|
|
|
|
++MII;
|
2010-11-16 05:20:45 +08:00
|
|
|
LocalMIs.insert(MI);
|
|
|
|
|
2014-03-14 02:47:12 +08:00
|
|
|
// Skip debug values. They should not affect this peephole optimization.
|
|
|
|
if (MI->isDebugValue())
|
|
|
|
continue;
|
|
|
|
|
2012-08-02 08:56:42 +08:00
|
|
|
// If there exists an instruction which belongs to the following
|
2014-04-03 06:59:58 +08:00
|
|
|
// categories, we will discard the load candidates.
|
2014-03-07 14:08:31 +08:00
|
|
|
if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() ||
|
2014-03-14 02:47:12 +08:00
|
|
|
MI->isKill() || MI->isInlineAsm() ||
|
2011-02-15 05:50:37 +08:00
|
|
|
MI->hasUnmodeledSideEffects()) {
|
2014-04-03 06:59:58 +08:00
|
|
|
FoldAsLoadDefCandidates.clear();
|
2010-11-16 05:20:45 +08:00
|
|
|
continue;
|
2011-02-15 05:50:37 +08:00
|
|
|
}
|
2012-08-02 08:56:42 +08:00
|
|
|
if (MI->mayStore() || MI->isCall())
|
2014-04-03 06:59:58 +08:00
|
|
|
FoldAsLoadDefCandidates.clear();
|
2010-11-16 05:20:45 +08:00
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if ((isUncoalescableCopy(*MI) &&
|
|
|
|
optimizeUncoalescableCopy(MI, LocalMIs)) ||
|
2012-08-17 07:11:47 +08:00
|
|
|
(MI->isCompare() && optimizeCmpInstr(MI, MBB)) ||
|
2015-01-13 15:07:13 +08:00
|
|
|
(MI->isSelect() && optimizeSelect(MI, LocalMIs))) {
|
2012-08-17 07:11:47 +08:00
|
|
|
// MI is deleted.
|
|
|
|
LocalMIs.erase(MI);
|
|
|
|
Changed = true;
|
|
|
|
continue;
|
2011-02-15 05:50:37 +08:00
|
|
|
}
|
|
|
|
|
[AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.
Examples:
1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
to b.<invCC>
2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
to b.<CC>
rdar://problem/18506500
llvm-svn: 219742
2014-10-15 07:07:53 +08:00
|
|
|
if (MI->isConditionalBranch() && optimizeCondBranch(MI)) {
|
|
|
|
Changed = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
|
|
|
|
// MI is just rewritten.
|
|
|
|
Changed = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2011-02-15 05:50:37 +08:00
|
|
|
if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
|
2010-11-18 04:13:28 +08:00
|
|
|
SeenMoveImm = true;
|
2010-08-10 07:59:04 +08:00
|
|
|
} else {
|
2012-05-02 07:21:41 +08:00
|
|
|
Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
|
2012-10-16 02:21:07 +08:00
|
|
|
// optimizeExtInstr might have created new instructions after MI
|
|
|
|
// and before the already incremented MII. Adjust MII so that the
|
|
|
|
// next iteration sees the new instructions.
|
|
|
|
MII = MI;
|
|
|
|
++MII;
|
2010-11-18 04:13:28 +08:00
|
|
|
if (SeenMoveImm)
|
2012-05-02 07:21:41 +08:00
|
|
|
Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
|
2010-08-10 07:59:04 +08:00
|
|
|
}
|
2011-02-15 13:00:24 +08:00
|
|
|
|
2012-08-02 08:56:42 +08:00
|
|
|
// Check whether MI is a load candidate for folding into a later
|
|
|
|
// instruction. If MI is not a candidate, check whether we can fold an
|
|
|
|
// earlier load into MI.
|
2014-04-03 06:59:58 +08:00
|
|
|
if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
|
|
|
|
!FoldAsLoadDefCandidates.empty()) {
|
|
|
|
const MCInstrDesc &MIDesc = MI->getDesc();
|
|
|
|
for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands();
|
|
|
|
++i) {
|
|
|
|
const MachineOperand &MOp = MI->getOperand(i);
|
|
|
|
if (!MOp.isReg())
|
|
|
|
continue;
|
2014-04-03 13:03:20 +08:00
|
|
|
unsigned FoldAsLoadDefReg = MOp.getReg();
|
|
|
|
if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
|
|
|
|
// We need to fold load after optimizeCmpInstr, since
|
|
|
|
// optimizeCmpInstr can enable folding by converting SUB to CMP.
|
|
|
|
// Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
|
|
|
|
// we need it for markUsesInDebugValueAsUndef().
|
|
|
|
unsigned FoldedReg = FoldAsLoadDefReg;
|
2014-04-14 08:51:57 +08:00
|
|
|
MachineInstr *DefMI = nullptr;
|
2014-04-03 13:03:20 +08:00
|
|
|
MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
|
|
|
|
FoldAsLoadDefReg,
|
2014-04-03 06:59:58 +08:00
|
|
|
DefMI);
|
|
|
|
if (FoldMI) {
|
|
|
|
// Update LocalMIs since we replaced MI with FoldMI and deleted
|
|
|
|
// DefMI.
|
|
|
|
DEBUG(dbgs() << "Replacing: " << *MI);
|
|
|
|
DEBUG(dbgs() << " With: " << *FoldMI);
|
|
|
|
LocalMIs.erase(MI);
|
|
|
|
LocalMIs.erase(DefMI);
|
|
|
|
LocalMIs.insert(FoldMI);
|
|
|
|
MI->eraseFromParent();
|
|
|
|
DefMI->eraseFromParent();
|
2014-04-03 13:03:20 +08:00
|
|
|
MRI->markUsesInDebugValueAsUndef(FoldedReg);
|
|
|
|
FoldAsLoadDefCandidates.erase(FoldedReg);
|
2014-04-03 06:59:58 +08:00
|
|
|
++NumLoadFold;
|
|
|
|
// MI is replaced with FoldMI.
|
|
|
|
Changed = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2012-08-02 08:56:42 +08:00
|
|
|
}
|
|
|
|
}
|
2010-01-13 08:30:23 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool ValueTracker::getNextSourceFromCopy(unsigned &SrcReg,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
unsigned &SrcSubReg) {
|
|
|
|
assert(Def->isCopy() && "Invalid definition");
|
|
|
|
// Copy instruction are supposed to be: Def = Src.
|
|
|
|
// If someone breaks this assumption, bad things will happen everywhere.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
assert(Def->getNumOperands() == 2 && "Invalid number of operands");
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
|
|
|
|
if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
|
|
|
|
// If we look for a different subreg, it means we want a subreg of src.
|
|
|
|
// Bails as we do not support composing subreg yet.
|
|
|
|
return false;
|
|
|
|
// Otherwise, we want the whole source.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
const MachineOperand &Src = Def->getOperand(1);
|
|
|
|
SrcReg = Src.getReg();
|
|
|
|
SrcSubReg = Src.getSubReg();
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool ValueTracker::getNextSourceFromBitcast(unsigned &SrcReg,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
unsigned &SrcSubReg) {
|
|
|
|
assert(Def->isBitcast() && "Invalid definition");
|
|
|
|
|
|
|
|
// Bail if there are effects that a plain copy will not expose.
|
|
|
|
if (Def->hasUnmodeledSideEffects())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Bitcasts with more than one def are not supported.
|
|
|
|
if (Def->getDesc().getNumDefs() != 1)
|
|
|
|
return false;
|
|
|
|
if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
|
|
|
|
// If we look for a different subreg, it means we want a subreg of the src.
|
|
|
|
// Bails as we do not support composing subreg yet.
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
unsigned SrcIdx = Def->getNumOperands();
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
|
|
|
|
++OpIdx) {
|
|
|
|
const MachineOperand &MO = Def->getOperand(OpIdx);
|
|
|
|
if (!MO.isReg() || !MO.getReg())
|
|
|
|
continue;
|
|
|
|
assert(!MO.isDef() && "We should have skipped all the definitions by now");
|
|
|
|
if (SrcIdx != EndOpIdx)
|
|
|
|
// Multiple sources?
|
|
|
|
return false;
|
|
|
|
SrcIdx = OpIdx;
|
|
|
|
}
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
const MachineOperand &Src = Def->getOperand(SrcIdx);
|
|
|
|
SrcReg = Src.getReg();
|
|
|
|
SrcSubReg = Src.getSubReg();
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool ValueTracker::getNextSourceFromRegSequence(unsigned &SrcReg,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
unsigned &SrcSubReg) {
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
|
|
|
|
"Invalid definition");
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
|
|
|
|
if (Def->getOperand(DefIdx).getSubReg())
|
|
|
|
// If we are composing subreg, bails out.
|
|
|
|
// The case we are checking is Def.<subreg> = REG_SEQUENCE.
|
|
|
|
// This should almost never happen as the SSA property is tracked at
|
|
|
|
// the register level (as opposed to the subreg level).
|
|
|
|
// I.e.,
|
|
|
|
// Def.sub0 =
|
|
|
|
// Def.sub1 =
|
|
|
|
// is a valid SSA representation for Def.sub0 and Def.sub1, but not for
|
|
|
|
// Def. Thus, it must not be generated.
|
2014-07-02 00:23:44 +08:00
|
|
|
// However, some code could theoretically generates a single
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// Def.sub0 (i.e, not defining the other subregs) and we would
|
|
|
|
// have this case.
|
|
|
|
// If we can ascertain (or force) that this never happens, we could
|
|
|
|
// turn that into an assertion.
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if (!TII)
|
|
|
|
// We could handle the REG_SEQUENCE here, but we do not want to
|
|
|
|
// duplicate the code from the generic TII.
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
|
|
|
|
if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// We are looking at:
|
|
|
|
// Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
|
|
|
|
// Check if one of the operand defines the subreg we are interested in.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
for (auto &RegSeqInput : RegSeqInputRegs) {
|
|
|
|
if (RegSeqInput.SubIdx == DefSubReg) {
|
|
|
|
if (RegSeqInput.SubReg)
|
|
|
|
// Bails if we have to compose sub registers.
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SrcReg = RegSeqInput.Reg;
|
|
|
|
SrcSubReg = RegSeqInput.SubReg;
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the subreg we are tracking is super-defined by another subreg,
|
|
|
|
// we could follow this value. However, this would require to compose
|
|
|
|
// the subreg and we do not do that for now.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool ValueTracker::getNextSourceFromInsertSubreg(unsigned &SrcReg,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
unsigned &SrcSubReg) {
|
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
advanced copy optimization.
This is the final step patch toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1
and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
into simple generic GPR copies that the coalescer managed to remove.
<rdar://problem/12702965>
llvm-svn: 216144
2014-08-21 08:19:16 +08:00
|
|
|
assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
|
|
|
|
"Invalid definition");
|
|
|
|
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
if (Def->getOperand(DefIdx).getSubReg())
|
|
|
|
// If we are composing subreg, bails out.
|
|
|
|
// Same remark as getNextSourceFromRegSequence.
|
|
|
|
// I.e., this may be turned into an assert.
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
advanced copy optimization.
This is the final step patch toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1
and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
into simple generic GPR copies that the coalescer managed to remove.
<rdar://problem/12702965>
llvm-svn: 216144
2014-08-21 08:19:16 +08:00
|
|
|
if (!TII)
|
|
|
|
// We could handle the REG_SEQUENCE here, but we do not want to
|
|
|
|
// duplicate the code from the generic TII.
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
TargetInstrInfo::RegSubRegPair BaseReg;
|
|
|
|
TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
|
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
advanced copy optimization.
This is the final step patch toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1
and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
into simple generic GPR copies that the coalescer managed to remove.
<rdar://problem/12702965>
llvm-svn: 216144
2014-08-21 08:19:16 +08:00
|
|
|
if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
|
|
|
|
return false;
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// We are looking at:
|
|
|
|
// Def = INSERT_SUBREG v0, v1, sub1
|
|
|
|
// There are two cases:
|
|
|
|
// 1. DefSubReg == sub1, get v1.
|
|
|
|
// 2. DefSubReg != sub1, the value may be available through v0.
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
// #1 Check if the inserted register matches the required sub index.
|
|
|
|
if (InsertedReg.SubIdx == DefSubReg) {
|
|
|
|
SrcReg = InsertedReg.Reg;
|
|
|
|
SrcSubReg = InsertedReg.SubReg;
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
// #2 Otherwise, if the sub register we are looking for is not partial
|
|
|
|
// defined by the inserted element, we can look through the main
|
|
|
|
// register (v0).
|
|
|
|
const MachineOperand &MODef = Def->getOperand(DefIdx);
|
|
|
|
// If the result register (Def) and the base register (v0) do not
|
|
|
|
// have the same register class or if we have to compose
|
|
|
|
// subregisters, bails out.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
|
|
|
|
BaseReg.SubReg)
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
// Get the TRI and check if the inserted sub-register overlaps with the
|
|
|
|
// sub-register we are tracking.
|
|
|
|
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
if (!TRI ||
|
|
|
|
(TRI->getSubRegIndexLaneMask(DefSubReg) &
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0)
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return false;
|
|
|
|
// At this point, the value is available in v0 via the same subreg
|
|
|
|
// we used for Def.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
SrcReg = BaseReg.Reg;
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
SrcSubReg = DefSubReg;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool ValueTracker::getNextSourceFromExtractSubreg(unsigned &SrcReg,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
unsigned &SrcSubReg) {
|
[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
advanced copy optimization.
This patch is a step toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov r0, r1, d16
but it does not understand yet
vmov.32 d16[0], r0
vmov.32 d16[1], r1
Comming patches will fix that and update the related test case.
<rdar://problem/12702965>
llvm-svn: 216136
2014-08-21 07:13:02 +08:00
|
|
|
assert((Def->isExtractSubreg() ||
|
|
|
|
Def->isExtractSubregLike()) && "Invalid definition");
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// We are looking at:
|
|
|
|
// Def = EXTRACT_SUBREG v0, sub0
|
|
|
|
|
|
|
|
// Bails if we have to compose sub registers.
|
|
|
|
// Indeed, if DefSubReg != 0, we would have to compose it with sub0.
|
|
|
|
if (DefSubReg)
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
advanced copy optimization.
This patch is a step toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov r0, r1, d16
but it does not understand yet
vmov.32 d16[0], r0
vmov.32 d16[1], r1
Comming patches will fix that and update the related test case.
<rdar://problem/12702965>
llvm-svn: 216136
2014-08-21 07:13:02 +08:00
|
|
|
if (!TII)
|
|
|
|
// We could handle the EXTRACT_SUBREG here, but we do not want to
|
|
|
|
// duplicate the code from the generic TII.
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
|
[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
advanced copy optimization.
This patch is a step toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov r0, r1, d16
but it does not understand yet
vmov.32 d16[0], r0
vmov.32 d16[1], r1
Comming patches will fix that and update the related test case.
<rdar://problem/12702965>
llvm-svn: 216136
2014-08-21 07:13:02 +08:00
|
|
|
if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
|
|
|
|
return false;
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// Bails if we have to compose sub registers.
|
|
|
|
// Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if (ExtractSubregInputReg.SubReg)
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return false;
|
|
|
|
// Otherwise, the value is available in the v0.sub0.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
SrcReg = ExtractSubregInputReg.Reg;
|
|
|
|
SrcSubReg = ExtractSubregInputReg.SubIdx;
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool ValueTracker::getNextSourceFromSubregToReg(unsigned &SrcReg,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
unsigned &SrcSubReg) {
|
|
|
|
assert(Def->isSubregToReg() && "Invalid definition");
|
|
|
|
// We are looking at:
|
|
|
|
// Def = SUBREG_TO_REG Imm, v0, sub0
|
|
|
|
|
|
|
|
// Bails if we have to compose sub registers.
|
|
|
|
// If DefSubReg != sub0, we would have to check that all the bits
|
|
|
|
// we track are included in sub0 and if yes, we would have to
|
|
|
|
// determine the right subreg in v0.
|
|
|
|
if (DefSubReg != Def->getOperand(3).getImm())
|
|
|
|
return false;
|
|
|
|
// Bails if we have to compose sub registers.
|
|
|
|
// Likewise, if v0.subreg != 0, we would have to compose it with sub0.
|
|
|
|
if (Def->getOperand(2).getSubReg())
|
|
|
|
return false;
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
SrcReg = Def->getOperand(2).getReg();
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
SrcSubReg = Def->getOperand(3).getImm();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
bool ValueTracker::getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg) {
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
assert(Def && "This method needs a valid definition");
|
|
|
|
|
|
|
|
assert(
|
|
|
|
(DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
|
|
|
|
Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
|
|
|
|
if (Def->isCopy())
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
return getNextSourceFromCopy(SrcReg, SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
if (Def->isBitcast())
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
return getNextSourceFromBitcast(SrcReg, SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// All the remaining cases involve "complex" instructions.
|
|
|
|
// Bails if we did not ask for the advanced tracking.
|
|
|
|
if (!UseAdvancedTracking)
|
|
|
|
return false;
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if (Def->isRegSequence() || Def->isRegSequenceLike())
|
|
|
|
return getNextSourceFromRegSequence(SrcReg, SrcSubReg);
|
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
advanced copy optimization.
This is the final step patch toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1
and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
into simple generic GPR copies that the coalescer managed to remove.
<rdar://problem/12702965>
llvm-svn: 216144
2014-08-21 08:19:16 +08:00
|
|
|
if (Def->isInsertSubreg() || Def->isInsertSubregLike())
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
return getNextSourceFromInsertSubreg(SrcReg, SrcSubReg);
|
[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
advanced copy optimization.
This patch is a step toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
bx lr
Indeed, thanks to this patch, this optimization is able to look through
vmov r0, r1, d16
but it does not understand yet
vmov.32 d16[0], r0
vmov.32 d16[1], r1
Comming patches will fix that and update the related test case.
<rdar://problem/12702965>
llvm-svn: 216136
2014-08-21 07:13:02 +08:00
|
|
|
if (Def->isExtractSubreg() || Def->isExtractSubregLike())
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
return getNextSourceFromExtractSubreg(SrcReg, SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
if (Def->isSubregToReg())
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
return getNextSourceFromSubregToReg(SrcReg, SrcSubReg);
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
const MachineInstr *ValueTracker::getNextSource(unsigned &SrcReg,
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
unsigned &SrcSubReg) {
|
|
|
|
// If we reach a point where we cannot move up in the use-def chain,
|
|
|
|
// there is nothing we can get.
|
|
|
|
if (!Def)
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
const MachineInstr *PrevDef = nullptr;
|
|
|
|
// Try to find the next source.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
if (getNextSourceImpl(SrcReg, SrcSubReg)) {
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// Update definition, definition index, and subregister for the
|
|
|
|
// next call of getNextSource.
|
|
|
|
// Update the current register.
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
Reg = SrcReg;
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
// Update the return value before moving up in the use-def chain.
|
|
|
|
PrevDef = Def;
|
|
|
|
// If we can still move up in the use-def chain, move to the next
|
|
|
|
// defintion.
|
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.
This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.
Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
into:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr
This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.
With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
PeepholeOptimizer::optimizeCoalescableCopy.
2. One for replacing non-generic copies with generic copies:
PeepholeOptimizer::optimizeUncoalescableCopy.
The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).
Both optimizations rely on the ValueTracker introduced in r212100.
The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.
Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).
Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.
This is related to <rdar://problem/12702965>.
Review: http://reviews.llvm.org/D4874
llvm-svn: 216088
2014-08-21 01:41:48 +08:00
|
|
|
Def = MRI.getVRegDef(Reg);
|
|
|
|
DefIdx = MRI.def_begin(Reg).getOperandNo();
|
[PeepholeOptimizer] Advanced rewriting of copies to avoid cross register banks
copies.
This patch extends the peephole optimization introduced in r190713 to produce
register-coalescer friendly copies when possible.
This extension taught the existing cross-bank copy optimization how to deal
with the instructions that generate cross-bank copies, i.e., insert_subreg,
extract_subreg, reg_sequence, and subreg_to_reg.
E.g.
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy b.sub0 <-- cross-bank copy
Would produce the following code:
b = insert_subreg e, A, sub0 <-- cross-bank copy
...
C = copy A <-- same-bank copy
This patch also introduces a new helper class for that: ValueTracker.
This class implements the logic to look through the copy related instructions
and get the related source.
For now, the advanced rewriting is disabled by default as we are lacking the
semantic on target specific instructions to catch the motivating examples.
Related to <rdar://problem/12702965>.
llvm-svn: 212100
2014-07-01 22:33:36 +08:00
|
|
|
DefSubReg = SrcSubReg;
|
|
|
|
return PrevDef;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// If we end up here, this means we will not be able to find another source
|
|
|
|
// for the next iteration.
|
|
|
|
// Make sure any new call to getNextSource bails out early by cutting the
|
|
|
|
// use-def chain.
|
|
|
|
Def = nullptr;
|
|
|
|
return PrevDef;
|
|
|
|
}
|